The 6502/816 chips can be stopped (RDY) and decoupled - tri-state'd (BE) from the system bus.

The '265's '816 core can only be stopped (BE/RDY) but not decoupled from the external bus but from its internal ROM, RAM and registers, so they can be inspected from an external debugging device.

In the Wait state information and uses for the BE pin section of the same document it's stated:


So...

I'm thinking in having the '265s access the internal Commodore 64 memory through its expansion port, and have the complete 64K memory of the computer mapped as one of the banks of 64K of memory.

For this to be able to be achieved, amongst several other things, the '265 should be able to be 3-stated, but AFAIK and what I put earlier, it cannot be done.

I was thinking in using the 74245 octal bus transceiver, or the 74640, the inverting bus transceiver, that should allow to remove the inverting gate just after the address bus.

So my question is:

Is it enough to decouple the ADDRESS bus from the system bus to avoid bus contention, or should I also decouple the data bus?

In another words: should I use just two transceivers (2 x 8bit address bus) or three transceivers (2 x 8bit address bus + 1 x 8 bit data bus)? As I only wanting to manage 64KB of memory, I would only need two transceivers for the 0-15 address bus lines, because the A16-A23 won't be used.

I want to use the '265 because I already have a clone of the 265SXB board working, so I have not to build another SBC with I/O and memory, and I have not to deal with demultiplexing the address bus as it comes natively 24 bit from the internal '816 core.

The Commodore 64 (for those not familiar with the computer) has the video chip and the cpu taking turns while accessing the memory. The video chip access it during the low phase of phi2, and the cpu access it during the high phase of phi2 (even the own video chips registers are accessed this way by the cpu).

But regularly the video chip needs several consecutive accesses to the memory and hence ask the cpu to stop and then makes it to decouple from the system bus, to avoid bus contention.

And as I need then to both stop the '265s (*) and decouple it from the system bus, and the chip won't do it, a transceiver it's needed.

So that's the question again: two transceivers or three transceivers?

Maybe the key here is what's also stated in the Data Bus (Dx) '265 datasheet section:


...just when the video chip access the system bus.


(*) well... its actually its internal 816 core, because the rest of integrated I/O still runs because the phi2 won't stop

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You're talking about contention between the '265 and the Commodore 64, is that right?

I'm not familiar with the details of the C64 expansion port, but I suspect you will, as you say, need to use three transceivers (2 x 8bit address bus + 1 x 8 bit data bus).

It'll be best to talk to someone who knows the ins and outs of that expansion port. And (just a suggestion) it might be a good idea to edit the subject of the lead post so it includes the words C64 expansion port.

BTW, do you have a block diagram of the proposed buses and control lines? This might be a useful aid to discussion.

-- Jeff

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Yes, actually... between the '265 and the VIC-II inside the C64. The rest of the chips only access the bus when the CPU pokes them.



Actually while the case is about the '265s and the C64, the example would apply to any other standard 6502 design, sporting a system bus.

What I'm trying to know is if the data bus lines are set Hi-Z too, after /OE goes inactive because the /CS line is pointed to a different chip. In another words: are all the chips in a computer receiving the values of the data bus, no matter if they are being selected? OR Do they set the data bus pins Hi-Z along with the address bus ones?



I think we can use the Commodore 64 CP/M cartridge as a reference, because it works sort of like what I', trying to achieve.



It seems that the C/PM cartridge used indeed the 76245 2x8 + 1x8 scheme. But its system bus pins are tri-state so maybe they are used here just like buffers.

Are you running the ‘265 or ‘816 at only 1 MHz?

I wonder if fast page mode can be used with the built in DRAM to allow access to more than one byte in a 1 MHz clock period, if the '816 were running at a higher clock. It would require more logic.

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Cannot tell, actually. I don't know if the DRAM chips of the '64 are fast page mode compatible, if they ought to be.