Aparently it's hip right now to be talking about 65816 based Systems, so i thought i'll share the plans i've been making about my own SBC.

Is the basic Idea is to make a recplacement for my current 65C02 SBC. it's great, but i'd like to explore the capabilities of the 65816 (and also just make use of more memory).
General component list:

• 65C816 (PLCC), I'm hoping for ~25MHz, but i'd also be fine with 12MHz
• 65C22 (PLCC), i did kinda regret not having one on my 65C02 SBC, so i'm including one now.
• SST39SF0x0 (DIP) for ROM, not all of it is used, more detail further below
• IS61C5128AL (SOJ) for RAM, 2 of these for a total of 1MB of SRAM. at 10ns they're fast enough for pretty much anything (and ironically they're cheaper than the 55ns AS6C4008)
• FT240X (SSOP) for Serial, good ol' reliable. like with my previous SBC i'll use USB-B for both Data and Power.
• DS1813, simple voltage based reset circuit, plus it auto debounce for a Reset Button, there is no reason to not include one of these
• ATF1508AS (PLCC), all the decoding logic and a few other features are within this one chip

Memory Map:

IO Map:


There are a few things about the Memory map that i want to point out.
Bank 0 is pretty barren. I tried to maximize the amount of useable RAM in Bank 0 because it's the only place for the Stack and Direct Page. and since i plan to mostly program this thing in C i want tthe stack to be as large as i can make it.
next, the ROM is split in 2. Bank 0 has a 256B piece of the ROM that is used to hold the Vectors and also switch the CPU into Native Mode upon power up, to then do a Long Jump to the actual ROM in Bank 1. This isn't even my idea to be honest, i don't remember where i read it but in one thread on here someone mentioned doing this with a ROM to save on space on Bank 0.
and lastly, the VRAM at the end of the Memory Map is not actually onboard. the Chip Select for that is simply passed to the Expansion Port for a future VGA Card. If i need the pin on the CPLD for something else i might just throw this one away and have the decoding on the Card.

Next up, the CPLD! the only Logic IC on the board.
It of course handles the Decoding Logic for the Memory and IO Devices, but also a few other features.

Clock Selector:
there are 2 Clock sources, a 24MHz Clock coming from the FT240X, and the other one coming from the Expansion Connector. (the main idea is that i wanted to avoid an onboard oscillator, mostly to save space)
the Control Register uses bits 3 and 4 to set which clock is used and if it's divided by 2 or not:


ROM Disable:
Because ROM is slow (70ns in this case) i wanted to have the ability to turn it off so i could run the CPU at faster speeds without the need for wait states or clock stretching whenver the ROM is accessed.
so, bit 5 of the Control Register can be set to disable the ROM completely, giving access to the RAM below. in addition while the ROM is enabled you can also Write to the RAM below it, so the idea is that shortly after startup the entire ROM would be copied to the RAM below, and then disabled.
I also thought about Write protecting the RAM as soon as the ROM is disabled, but i decided against it for now. if i feel like it's worth it i can always re-add the functionality.

Timer Interrupt:
One of the main reasons i wanted to include a 65C22 was because of the T1 Timer, but with my planned CPU Speeds (24MHz) it would be limited to a ~2ms Periodic Interrupt, which is way too fast.
But i realized that instead of an Interrupt you can have the T1 Timer flip the value of PB7 everytime it resets. so my idea was to take that pin and directing it into the CPLD, which has a small internal counter that increments each rising edge, after 10 Increments it resets itself and sends an Interrupt to the CPU (which can be toggled with bit 2 in the Control Register).
basically it's like using the T1 Timer Interrupt but multiplied by 20, so i can use much smaller values in the VIA Registers.
Honestly i wish the VIA just had an Internal Clock divider or atleast the ability to use an External Clock for T1.

Status Register:
Reading from the Control Register reads back the 4 bits mentioned above, but it also reads 2 control signals from the FT240X that tell you the state of the Sending/Receiving FIFOs.
to recap:


And lastly there are a few things i wanted to ask about:
I have Port A of the VIA (plus CA1 and CA2) hooked up to a Pin Header, so i can use them for whatever. meaning that i only have Port B available for onboard stuff.
and i was thinking of having an onboard PS/2 Connector for a Keyboard and deal with it in Software. but what exactly would be the best way of doing this? my idea was to use one of the CB pins to cause an Interrupt when the PS/2 Clock goes low the first time, and then sit in the ISR and check the Clock and Data pins until it's done, saving the result in some buffer somewhere in Memory.

And something that i think would be good for another thread: dealing with a PS/2 Mouse. I never really found anything about using a PS/2 through a VIA so that would be an interesting topic, not just about the Mouse itself but also how to deal with both a Keyboard and a Mouse in the same VIA, how you hook both of them up, how a read out routine for either would look like, and maybe even how to handle the edge cases of both checking the mouse and a keypress coming in at the same time. (I'd say the keyboard should take priority, but maybe someone else have a different idea)

another thing i wanted to ask about:
I've heard that full Address/Data Busses being on the Expansion Connector isn't the best thing for speed, but my 65C02 runs stable at 20MHz despite the Address/Data Busses being on the Expansion Connector
So is the speed impact a lot smaller than i thought, or did i just get lucky because the Connector is right next to the CPU?
since i'm aiming for similar speeds i'm currently just hoping that it will work out the same way by just having the Expansion Connector between the CPU and CPLD/Memory.
plus this Expansion connector has extra 5V and GND lines spread across the whole thing, so i hope that also helps for when something is actually plugged in.

the PCB layout is pretty much done, but the routing and Schematic aren't, because assigning pins to things that don't require an exact pin order (RAM, Expansion Connector, CPLD) take longer for me to do because i first need an idea of how they are placed on the PCB so i can choose the pins to have the shortest and least spaghetti-like path.
This is what the PCB currently looks like:

I'm really proud that i was able to fit all of this into 10x10cm (it's 9.96x8.89cm). but i'm also scared that the compactness is going to be an issue in the future somehow.
i'm also kinda considering makes this my first 4 layer PCB, just for the extra GND and 5V Layers, but i'll likely keep that for a revision 2 in case there are mistakes in this one that would have me order new PCBs.

So, that's it right now, leave your thoughts below!
Maybe there is something critial i'm overlooking or missing, maybe i should have fewer Power lines on the Expansion Port to make it smaller, maybe there is something i shouldn't include on the board, maybe there is a better way to order things on the PCB... lots of things i could've not thought about. but that's why i'm posting it. so have fun tearing this apart!

I'm not qualified to answer your questions, but I would like to congratulate you for a tidy and attractive board. I'm interested to see how fast it'll clock with two layers.

_________________
Got a kilobyte lying fallow in your 65xx's memory map? Sprinkle some VTL02C on it and see how it grows on you!

Mike B. (about me) (learning how to github)

I agree with Mike... nice tidy layout. However, I'm guessing it's incomplete... as there's only 5 bypass caps, no debounce on the NMI trigger and perhaps more (without a schematic, hard to tell).

A few suggestions:

- use a larger header for the VIA Port A. As it stands, you don't have a ground pin, so there's no reference for using any of the VIA lines. Daryl used a 14-pin 2-row header on his SBC 2.5 board which includes ground and Vcc pins, so you can do something useful with a single ribbon cable. I copied it for an older serial/parallel adapter many years ago, it allowed me to so some simple experiments, easily.

- think about using more SMT parts... as you're already using a few, why not extend that with the ATF 1508, W65C816 and W65C22? Using a PLCC version of EEPROM would also save some space.

- I would add a larger reservoir capacitor (or 2), something in the 50-100 uF range.

- I would add more bypass caps... quite a few more!

- I would include a small (8-pin DIP) format clock oscillator as a safety...

- I would just go with a 4-layer PCB layout up front.

- maybe add a power switch? can't easily tell if there is one or not.

A schematic would be helpful for any additional suggestions.

As for the full address bus on the expansion connector. That really depends on your future plans. My older C02 Pocket SBC only has 5-address lines on a 30-pin expansion connector, but also has 4- I/O selects, each can be 32 bytes wide, which can accommodate a fair number of I/O devices. Attached image just for reference, as the '816 bus would likely have some different signals required.



As for the PCB board size... small is beautiful! My C02 Pocket is 3.8" x 2.5", which is truly is "pocket size"! Smaller PCB also means shorter traces, which is good as you want to run at higher clock rates.

Keep us posted!

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Regards, KM
https://github.com/floobydust

I'd also suggest the 4 layer route. I just ordered 5 10cmx10cm 4 layer boards from JLCPCB and it only cost $8.

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Bill

You have a 128-macrocell ATF1508 that's hardly utilized, personally I'd replace 6522 with sparsely utilized and much more flexible ATF1508. You may not want to get rid of 6522, but then ATF1508 can easily do PS2 keyboard, I2C, SPI, W2812B, timer interrupt, LCD display functions and probably more. Bring out unused ATF1508 pins to group of jumper pads, be sure to add power & ground pins. You'll find uses for these spare pins sooner than later.

Expansion connector should work fine in 100mmX100mm size pc board. I'd go full 100mm X 100mm and design it for an existing enclosure. (My favorite nowaday is Pactec CM5-200, perfect for 100mm X 100mm pcb). 100mmX100mm 4-layer PCB is so cheap now I wouldn't bother with 2-layer PCB.
Bill

Thanks to both of you, i didn't think i'd be able to make the PCB look half decent with so little space.


- Hmm, i do have a bit more space to play with, so i could extend the PCB downwards to be pretty much a square and move the buttons down a bit too, then i fit a 2 row Header.

- i don't like not being able to remove ICs, the fact that i loose an FT240X and some RAM ICs everytime i retire one of these boards is already painful enough (I don't have the equipment for desoldering), plus there is overall a greater chance of screwing up SMT soldering, and that is not worth loosing something as expensive and annoying to buy as a CPU, VIA, or CPLD.
but i can do all bypass caps as SMT to free up a bit more space for Traces, since i'll just let JLCPCB solder those for me.
also i knew the SST39SF0x0 series also came in PLCC Package, but i thought those were 3.3V only. i just checked Mouser and they also sell 5V Versions for like 2 EUR. so i'll order a few of those and update the schematic and PCB.

- Yes i definitely need some large cap near the Power input

- Well it was mostly a space issue, but since i'll be re-doing those as SMT i think i'll be able to fit a few more. do you have some general rules for bypass caps other than placing them near the power pins of ICs?

- nope, that's exactly what i want to avoid. if the FT240X is somehow broken i'll just temporarily solder a wire onto the bottom of the CPLD's Clock input.

- i kinda want to try it, but i'm also scared because that's a lot of money and waiting for a potentially bricked PCB. but if i were to do it i would put the signal layers on the outside so that i can cut traces and add botch wires if necessary.

- There is a Power switch in the very top left next to the USB Connector.


well even if i did finish it it likely wouldn#t be that helpful because i'm using tunnels for pretty much everything.
once i got stuff finalized i'm gonna make a copy of it and try ot beautify it a bit.


I want to be able to Expand Memory in the future, so i can't really get around having all of the Address Bus. oh well.


that is tiny, very impressive. and yes i'll try to keep you guys updated.


uhm, how do you define "hardly utilized"? this thing is pretty full in terms of IO



I did think about adding a 65SPI and 32 bit Timer into the CPLD, but due to the lack of available pins (and Macrocells) i had to completely scrap the idea and just go a VIA and my weird x20 Interrupt Timer circuit. I might have a 65SPI core as an Expansion Card in the future. maybe a multi IO card with VGA, PS/2 Mouse, and a 65SPI Core all in one.


hmm, i'll just have to see what price JLC spits out for me...
also doing exactly 100x100mm seems like a good idea, that should be easy to change

Nice looking board, and thanks for the specs and particulars!



I traditionally use CA1 for PS/2 Keyboard Clock, and PA7 for PS/2 Keyboard Data. I don't use the BIT instruction currently but you can and it would work well with that situation. Very easy to set up! Ben Eater's video on Keyboard Interfacing was very helpful.



I have been doing some reading recently on the PS/2 Mouse. I currently have the DIN-6 currently set for Keyboard as primary, and the unused pins are for the Mouse. Reference the Wikipedia "PS/2 Port" page for pinout. If you plug a Keyboard in directly, it works as expected. Plug a mouse in directly, and it runs 'like a keyboard', so you can switch over in software if you like (in theory). BUT, if you use a PS/2 Y Splitter, you can put both Keyboard AND Mouse on the same DIN-6 connector. This is what I'm planning on doing, and will use CA2 and PA6 for the Mouse Clock and Data (respectively). *PLUS* the mouse apparently needs you to send data back to it, so you must be able to change the clock on the host side. Thus CA2 is preferred, and not CA1. The keyboard does not need you to send anything back, unless you want the Caps Lock light to turn on or something. If you want to use CB1 and CB2, same applies.

Looks great Proxy, thanks for sharing!

Chad

Update!

I Finished the PCB and cleaned up the Schematic a bit. technically i'm ready to order the PCBs but i'll look everything over again to really make sure i didn't miss anything.

I originally wanted to replace the current bypass caps with SMT ones, but the setup fee for JLC soldering those would've cost as much as the board itself, so i went back to TH and just added a few more caps.
the Expansion connector was moved to the right edge of the board because having it in the middle screws too much with the routing, the board is small so it shouldn't cause an issue.
I added the debounce cap to the NMI Button, and a 100uF Elec. Cap to the Power input.
the PS/2 Connector now is hooked up to the VIA to allow a Y Splitter to be used for both a Keyboard and Mouse at the same time, with the Keyboard Clock also going to CB2, while the Mouse Clock also goes to CB1.
and lastly I also added a socket for a Oscillator even though i really didn't want to... but i can see the reasons to have one anyways and there was enough space to fit it.
I even made use of my Custom Footprint that allows for both DIP-14 and DIP-8 Oscillators to be inserted:

(the arrow points to the pointy corner of the Oscillator, aka Pin 1)

So here the new PCB:

i also added a tiny smiley face on the backside where the CPU Socket is, it's for added performance and good luck

and finally the Schematic, both in color and BW:

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Your NMI and Reset circuits both need attention. There are various solutions. For example, a DS1813 can be used to debounce. But here's another approach (as documented in Garth's primer).

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

well i have used JLC's SMT assembly service before.
once for an Arduino-like MCU board around the AVR128DB48 because it just came out and i wanted to experiment around with it.
and also for a FPGA Breakout board (MachXO2-1200HC).

both mainly just had passive components (plus a 3.3V Voltage Regular for the FPGA Board and an FT232RL for the MCU Board) done by JLC.
from what i remember from those orders there is a one time "setup fee" for choosing SMT assembly, and then it just adds the cost of each component to be soldered. the parts are split into 2 categories, basic and extended. basic parts are most commonly used ones like passives while extended parts cost an extra 1 time fee and are used for more uncommon or more expensive parts like a lot of ICs.
so i'd say it's only really worth it when you have a lot of parts on a PCB or want to order a lot of PCBs.
though i cannot tell you how the setup fee scales with the size of the PCB or the amount you order. but atleast it seems that both 2 and 4 layer PCBs have the same starting fee of 8 USD.



Why the reset circuit? it's identical to how it is on my 65C02 SBC and it lines up with example in the datasheet of the DS1813:

I did think about using a second DS1813 for the NMI Circuit, but i'd have to order a few new ones so i thought i could just use a regular debounce circuit.
speaking of which, what exactly is wrong with the debouncing on the current NMI circuit? (i already noticed that C13 should be going to GND not 5V, is anything else wrong with it?)

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

sadly i don't have any 3.3k Resistor networks, the kit i have only uses 2 base values. so it goes 470 -> 1k -> 4.7k -> 10k -> 47k.
So i'll put that on the shopping list for later.


hmm, there are only 2 signals from the CPLD that go to the VIA: SYS_CLK and ~CS_VIA. I can free up some space on RN0 to fit those on there...
NMI no longer needs a pull up due to being powered by the DS1813, and it should be fine to directly wire ~ABT to 5V since unlike RDY it's only ever an input.

I'll have to do some rerouting to make those changes possible

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

alright so i gave NMI, RST, and ABT their own 3.3k pull ups. i just used seperate resitsors because i didn't want to bother with another resistor array.