Board looks good. Nice and dense.

Is there a bypass capacitor on both sides of the 65C816's socket? Can't tell in the photo.

I’ve never been able to figure out how a standard that has eight or nine different and incompatible connectors can call itself “universal.”

I’ve never been able to figure out how a standard that has eight or nine different and incompatible connectors can call itself “universal.”

there are basically just 3 connectors that really matter today

I have current-production devices with five kinds, plus the bigger kind that the PC has several of.

Several kinds of connectors have been used for RS-232 also; but you can make up your own cables for that on the workbench. You can't do that with USB.

anyways, bit more on topic, the speaker circuit is a bit confusing to me. why is there a jumper for the volume instead of a potentiometer?
I'm a novice when it comes to analog circuitry and anything transistor related, so maybe there is a technical reason? or did you just want to avoid having to buy extra components?

And the transistors before every LED and button confuse me a little as well, does it help with keeping the current load off the CPU pins, or make the signal/voltage more stable?

I'm also a bit surprised by the fact that there is pretty much no exposed IO besides the SPI.
like i feel like you could've squeezed in a header for all the unused VIA Pins so you can experiment with various hardware on a bread- or perfboard.

but besides that it's a very clean looking board!

Yeah, I wasn't sure about this - but rather than taking the chance of messing with the system signals I just thought better to be safe than sorry.

They are configured correctly, but the 1K resistor will make for over 4mA of base current, which is way, way more than you need. The LED resistors are 300 ohms which, with about 3V across them, will make for 10mA through the LED which with modern LEDs is just blinding. That's ok for something like the IRQ LED which might be on for such short times it might otherwise be hard to see; but for anything that's going to be low for longer, I would put maybe a 1K resistor in series with the LED, for about 3mA; then with the transistor beta of 80 minimum, you'd only need 37 microamps base current. You could even triple that to 111uA which you could get with 39K, a much lighter load on the line.

You are likely running into timing issues with the flash ROM at 14 MHz. You didn’t mention wait-stating in your earlier posts, something you would likely need to get into the 14 MHz range. There are topics around here that discuss wait-stating as it pertains to the 65C816.

Bottom line is I think you are being limited by the ROM. If you have a suitable oscillator, see if you can get it to boot at 12 MHz.

Using a scope alone to determine if the ROM is stumbling would be somewhat awkward, although not impossible. The logic analyzer (LA) would be more helpful in that regard. It would be profitable to get proficient with the LA if for no other reason than to observe the circuit in action and become acquainted with what is going on as the 65C816 goes about its business.

Basically, you want the LA to look at when the ROM's /OE is asserted relative to the clock cycle, as well as observe when the ROM actually drives the data bus. That will tell you at what point in the read cycle the 816 will “see” the ROM’s output Since the ROM’s /OE must not be asserted during Ø2 low to avoid data bus contention, the ROM has less than half the total Ø2 cycle to respond to /OE and drive the bus. Specifically, it has to be able to satisfy the sum of the 816's tDSR (read data setup) and tDHR (read data hold) timing specs to guarantee that the data read is reliable. If the ROM can't meet that requirement, the circuit may become unstable or may fail to boot.

It’s important to understand that the 816 reads or writes data at the fall of the clock. tDSR is a period of time that precedes the fall of Ø2 and tDHR is a period of time that will elapse after the fall of Ø2. During a read cycle, the 816 will open its data latches no more than tDSR nanoseconds before the clock falls and capture whatever is on D0-D7. Ideally, the data latches would close at the fall of the clock, but in practice they will lag the clock by a couple of nanoseconds. Hence tDHR is specified to assure D0-D7 will remain stable until the latches are closed.

Officially, tDSR and tDHR are both 10ns minimum when operating on 5 volts—note that these values are independent of the actual Ø2 rate. In practice, you can fudge those numbers to some extent, since the 816 actually performs significantly better than the data sheet would lead you to believe. The 0.6µ cores that have been in production for the last 15-or-so years are capable of operating beyond 24 MHz on 5 volts, based on extrapolation of the published FMAX vs. VDD curve. This being the case, most of the critical timing minimums appear to be about 60-70 percent of the quoted values. Ergo tDSR and tDHR would be more like 6-7ns each, which would give your ROM a little more “headroom.”

To what would you wire it? In my circuit, the 109 is used as a one-shot timer that controls the clock generator flip-flop. By itself, it wouldn’t do anything for you.

The 28L92 will function in a system running at 14 MHz—at least in my POC units, but timing can be touchy at that point. If you can, you should arrange both ROM and I/O accesses (other than the 65C22) to be wait-stated. You really need a more sophisticated clock generation setup to successfully implement wait-states via clock-stretching.

Ultimately, the efficiency of your glue logic will set a hard limit on performance. That you have the entire 16-bit address bus wired to the CPLD makes me wonder just how well this will work at double-digit clock rates.

One more thing...RAM and ROM generally perform best if /CS os asserted before /OE or /WE (RAM) are asserted. In other words, your glue logic should assert the appropriate /CS as soon as the 816 indicates it has a valid address on the data bus. That gives the selected device about one-half of Ø2 low to come out of catatonia and get ready for access.