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PostPosted: Sat Jun 04, 2022 2:15 am 
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Why does this instruction add one to the accumulator if the carry flag is set?

Code:
ADC #$0000


I looked at the ADC page in Eyes & Litchy about this, and get the impression that the reason is to make multi-word addition easier. But this makes it harder to add things of the processor's native register size, because I have to remember to CLC beforehand if I don't want the result to be one greater. Is it really that common to do multi-word addition on these processors?


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PostPosted: Sat Jun 04, 2022 2:21 am 
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Because the word size is so small, yes, it's very, very common to handle numbers of larger than native size. Other architectures have taken other approaches to this over the years (providing separate add-without-carry instructions, or simply saving carry-out so that the programmer can handle carry-in if desired,) but the 6502 was designed with a pretty minimalist mindset, and if you have to choose just one approach to handle both word-sized and extended operations, this isn't a bad one.


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PostPosted: Sat Jun 04, 2022 2:28 am 
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I see. It doesn't seem quite as valuable on the 65816 when the accumulator is 16-bits.


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PostPosted: Sat Jun 04, 2022 4:01 am 
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jeffythedragonslayer wrote:
I see. It doesn't seem quite as valuable on the 65816 when the accumulator is 16-bits.

What do you mean by that? Carry functions the same regardless of the accumulator size and has the same importance to both addition and subtraction as when processing eight bits at a time.

commodorejohn wrote:
Other architectures have taken other approaches to this over the years (providing separate add-without-carry instructions, or simply saving carry-out so that the programmer can handle carry-in if desired,)...

The 6502 family’s ancestor, the 6800, had both ADD and ADC. As you noted, the 6502 design was tailored to fewer instructions as part of the drive to get down the cost, so eliminating the semi-redundant ADD was logical.

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PostPosted: Sat Jun 04, 2022 4:39 am 
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Many newcomers have wondered why there aren't add & subtract without carry instructions; but note that especially on the '816 where the op code table is completely full partly because of the many addressing modes, there are no op codes left for these unless two-byte op codes were to be used. (Actually, the WDM op code was reserved for future expansion into a second table of 255 op codes, but it was never done.) As it is, the '816 has 15 addressing modes for ADC and 15 for SBC; so to have all the same addressing modes for add and subtract without carry as well would require 30 more op codes. I learned 6502 first and later PIC16, and the latter only had add and subtract without carry which I found to make things far less efficient than the 65xx way, in bytes and cycles both.

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PostPosted: Sat Jun 04, 2022 4:41 am 
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BigDumbDinosaur wrote:
jeffythedragonslayer wrote:
I see. It doesn't seem quite as valuable on the 65816 when the accumulator is 16-bits.

What do you mean by that? Carry functions the same regardless of the accumulator size and has the same importance to both addition and subtraction as when processing eight bits at a time.

Yeah, multi-precision arithmetic is still important in 16 bits. 32 bits is about the smallest word size (well, in modern multiples-of-8 convention) where you can do many tasks of meaningful complexity without having to deal with larger integers at some point, and even then it's hardly uncommon.


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PostPosted: Sat Jun 04, 2022 8:39 am 
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Here are two ways to think of the question
- why does the 6502 have only ADC, and no ADD
- if only one, would it be better to have only ADD

For the first, it's because, as noted up-thread, it's a minimal machine, designed specifically to have a much reduced cost and therefore much reduced price. As much as 10x lower, which is to say, a 90% discount on the competition.

For the second, it turns out that having only ADD without ADC makes multi-word arithmetic quite cumbersome - it can be done, and it has been done, but it's easy to get it wrong.

And indeed, at 8 bits and even at 16 bits, multi-word values crop up often enough. Bearing in mind that the sort of embedded application envisaged for the 6502 would have multi-digit displays (weighing, measuring, point of sale) we see that many customers would have wanted both the multi-word arithmetic and the decimal mode.

The origin story of the 6502 is the idea that the 6800 particularly was too expensive, and most customers would have been happy to have a simpler microprocessor if it could be cheaper. As Motorola didn't agree, and would put it in writing as an abandoned idea, the 6502 team felt able to go off to build that simpler microprocessor. As it turned out, one junior person did bring some 6800 artwork with them, which made the subsequent lawsuit more sticky, and the effect was to have the 6501 withdrawn, and for MOS technology to need a lot of cash, which is where Commodore came in to buy them up.


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PostPosted: Sat Jun 04, 2022 8:58 am 
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commodorejohn wrote:
Yeah, multi-precision arithmetic is still important in 16 bits. 32 bits is about the smallest word size (well, in modern multiples-of-8 convention) where you can do many tasks of meaningful complexity without having to deal with larger integers at some point, and even then it's hardly uncommon.

Excepting timestamp fields, my 816NIX filesystem that is under development uses 32-bit, unsigned integers to describe all internal relationships. This works out well with SCSI-2 logical block addresses, which can be 21-bit or 32-bit, the latter being necessary once disk capacity exceeds a gig. A 32-bit LBA can address several terabytes on a single disk, well beyond anything I would ever need.

In order for all this to work, I developed a math package that accepts 32-bit operands and will produce 64-bit results. I basically scaled up older code I had written for the 65C02, using the 65C816’s 16-bit capabilities to shrink routines and speed up things.

Incidentally, Supermon 816 uses 32-bit integers as well. The 816 can only address 16 MB, which is representable in 24 bits. However, processing 24-bit integers is inefficient, due to the need to constantly change the size of the accumulator during arithmetic operations. So I wrote Supermon 816 to use 32-bits as the default integer size, which means the low-level arithmetic functions can keep the accumulator set to 16 bits.

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PostPosted: Mon Jun 06, 2022 2:09 am 
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BigDumbDinosaur wrote:
jeffythedragonslayer wrote:
I see. It doesn't seem quite as valuable on the 65816 when the accumulator is 16-bits.

What do you mean by that? Carry functions the same regardless of the accumulator size and has the same importance to both addition and subtraction as when processing eight bits at a time.

It appears to me that ADC was designed this way on the 6502 to make multi-byte addition easier to do (since it's so common on an 8-bit machine) at the expense of making single-byte addition harder: you need to remember to CLC beforehand or otherwise convince yourself that the carry flag is unset in order to get the correct answer when working with just 8-bit addends.

But when your processor's sizeof(int) suddenly == 2 (when you upgrade to the 65816 and are porting software over to take advantage of the 16-bitness) there are often going to be fewer addition situations that are multi-word, so this design tradeoff doesn't buy you quite as much.


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PostPosted: Mon Jun 06, 2022 2:34 am 
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In some cases you'll already know the state of the carry flag, so you might not have to do CLC or SEC. For addition, obviously "clear" is the preferred starting point; but even if you know it's set (from a previous operation, even if it wasn't an addition or subtraction), and you're going to add a constant, you can make the constant to be one less than you otherwise would have.

In any case, CLC only takes one byte and two clock ticks. A lot of the 6502's contemporaries couldn't do anything at all in two clock ticks.

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PostPosted: Mon Jun 06, 2022 5:47 am 
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jeffythedragonslayer wrote:
It appears to me that ADC was designed this way on the 6502 to make multi-byte addition easier to do (since it's so common on an 8-bit machine)...

ADC exists in the MC6800, which is the ancestor of the 6502. MOS Technology didn't “design this way”—they copied a competitor’s existing operation and even used the same mnemonic. An objective of the 6502 design team was to make it reasonably painless for 6800 users to migrate to the 6502. Trying to create equivalents to 6800 instructions helped in achieving that goal.

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...at the expense of making single-byte addition harder: you need to remember to CLC beforehand or otherwise convince yourself that the carry flag is unset in order to get the correct answer when working with just 8-bit addends.

I think you are going around in circles here.

Another objective of the 6502 designers, and one that was very important in the scheme of things, was to undercut the cost of the 6800. To do so, it was necessary to get the die size down, which was accomplished by eliminating instructions that could be readily synthesized with other instructions. Such was the case with ADD.

Use of CLC before ADC is not “harder.” Just how difficult is it for you to type the letters C, L and C? And, as Garth noted, the effect of CLC on the performance of the program is very small. Two Ø2 cycles on a 65C02 or 65C816 running at 20 MHz is 100 nanoseconds. Also, there is a good possibility carry will already be cleared as a result of a previous operation. It’s all a matter of knowing the assembly language and carefully planning your program to minimize the number of instructions needed to accomplish something.

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But when your processor's sizeof(int) suddenly == 2 (when you upgrade to the 65816 and are porting software over to take advantage of the 16-bitness) there are often going to be fewer addition situations that are multi-word, so this design tradeoff doesn't buy you quite as much.

Just how much 65C816 software have you written in assembly language? At the risk of being offensive, I think your statement is completely illogical.

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PostPosted: Mon Jun 06, 2022 2:15 pm 
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I don't find it at all illogical to expect fewer multi-precision additions when the word length doubles. Just my $.02 worth...

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PostPosted: Mon Jun 06, 2022 2:19 pm 
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Fewer, sure. But hardly none, especially when "doubled" is still only 16 bits.


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PostPosted: Mon Jun 06, 2022 5:23 pm 
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Having the 16-bit registers of the 65C816 encourages one to work with larger data structures, which often entails the use of double words and “long” pointers. So there are just as many opportunities for multi-word addition and subtraction with the 816 as there are opportunities for multi-byte additions and subtractions with the 65C02.

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Last edited by BigDumbDinosaur on Tue Jun 07, 2022 1:32 am, edited 1 time in total.

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PostPosted: Mon Jun 06, 2022 5:28 pm 
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I hope you're not discouraged, jeffythedragonslayer, by the strongly-expressed opinions upthread. It's not how we usually conduct ourselves here.


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