Thanks for the warm welcome, guys!
So nice to see such an active retro forum as this, can't believe I didn't look into 65xx before - guess I was just so fascinated by x86 since that's what I grew up with in the mid-80's.
jmthompson wrote:
What is your concern about the timing on the bank address?
Not the bank address specifically, just everything in general. I was kind of intimidated by watching Adrien Kohlbecker's youtube videos going into details about timing requirements.
jmthompson wrote:
Your I/O ranges are awfully big, though I understand it uses less logic to decode fewer bits. Generally I make my I/O ranges 32 bytes, which is already twice as big as the register window of your VIA or UART.
Yeah I know they're wastefully big ranges. As you say, it's for saving decode bits. I'd like to keep all of that stuff in the 22v10 if possible, and I'd only save 2-3 KB if using one or two extra address lines anyway.
Edit: Did my math wrong, I'd be saving 4-6 KB, maybe worth looking into actually!Edit2: Yep, that compiled just fine in WinCupl. Had to remove VPA, but as I understand it, that will still be perfectly adequate, using only VDA for IO qualifying.jmthompson wrote:
The clock should qualify both /RD and /WR.
Yep, I've changed the PLD code to include CLK qualifying the /RD as well, thanks!
BigDumbDinosaur wrote:
I’d keep RN1. However, its common connection should be to VCC, not ground. RN1 will prevent the data bus from floating when the bus transceiver is in the high-Z state, which condition could theoretically inject noise into the system. With RN1's common at VCC instead of ground, devices with TTL outputs, e.g., the SRAM, will have less work to do in getting the data bus up to a solid logic one. TTL outputs are generally able to pull down harder than up, so the resistor will add negligible burden.
That's interesting, I'll definitely make that change! As for pull-up strength, would it make sense to raise the R a bit? Isn't 1k a bit low as far as pull-ups goes for an application such as this...?
BigDumbDinosaur wrote:
I recommend you place a 100 µF low-ESR electrolytic in parallel with C19. Both capacitors should be as physically close to the MAX238’s VCC pin for best operation. It’s best to keep the traces between the charge pump caps and the MAX238 as short as possible.
Good idea!
BigDumbDinosaur wrote:
R16 is unnecessary. Instead, connect the DUART’s X1 clock input (pin 36) to VCC through a 470 ohm resistor, per the NXP data sheet.
Ah yeah, I missed that from the datasheet, thanks!
BigDumbDinosaur wrote:
You’ve got SPKR connected to the 65C22 and to the DUART. Is that intentional?
It is most definitely not!
I have no idea how that got in there! Should only be connected to the 65C22.
BigDumbDinosaur wrote:
If possible, outputs OP4-7 of the DUART should be reserved for future use. I use them in my designs as channel-specific IRQ outputs to improve the performance of the data I/O parts of my interrupt handler.
Care to explain this a bit further? How would these channel-specific IRQ's be read by the '816 with its single IRQ input?
BigDumbDinosaur wrote:
So when do you plan to build it?
As soon as possible!
Need to order most of the parts and do the PCB layout, then I'll get it made by JLC (whom I've used lots of time in the past with great success).
Very reassuring to have y'all give me the thumbs-up first!
I've updated the schematic, will replace some of the resistors with networks if needed for space later.
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