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Wolftronics? I'm asking for a friend who is also a sheep.
I apologize for some of the regulars who claim your work was obtuse. I found your board layout almost self-documenting. Only minor details required reference to the very tidy schematic and the memory map provided a very concise overview. Indeed, in addition to your memory map being KIM-1 and Apple I compatible, I believe that your design is also W65C265 compatible.
Your double ATX board is possibly the largest design on the 6502 Forum. Correspondingly, it may be the most expensive. I tried getting a similar size board game manufactured as a PCB. Due to the lack of component footprints, JLCPCB rejected the design. PCBWay quoted USD80 per board for a minimum of five boards. It would be very worthwhile to design a single ATX board (or smaller) with hardware compatible fixing holes and slot positions.
I don't recommend expansion cards because they adversely affect maximum clock speed but if you're determined to use a card format, jfoucher's Planck bus is popular and I believe that it is licence compatible with your work. Planck bus is intended to provide 16 byte peripherals in the first half of page $FF and the cards are electrically safe if accidentally reversed. This could be extended with an asymmetric, keyed section to provide more address lines. Suitable cards could work in both systems. In your case, a host may be devised which allows short cards to present one 6522 or similar. Meanwhile, long cards may use a much larger section of the memory map.
It is a pleasure to see someone attempt a full 7805/7812/7912 linear PSU; especially for fully conformant 65SIB. After sparking a switch mode PSU and destroying, I made a bare 7805 and left space for 7812 but never implemented that section. Given that the 5 volt section of ATX PSU is the least likely part to persist future revisions of the standard and the most likely part to get destroyed with experimental hardware, it may be prudent to Buck convert and linear smooth 12V to 5V.
I believe that the self-certified European regulations which were valid until 2017 required 1mm track spacing for mains power. I presume that the spirit of the regulations was to make the separation larger the radius of any condensation. This isn't a problem if a board is lacquered or the tracks are on inner layers. However, I strongly recommend 3mm separation around mains power solder joints.
I like your interrupt mask and you are wise to present even values for JMP (abs,X). One additional signal should be brought to the register such that spurious interrupts may be directed to a ninth vector. Unfortunately, the 74x148 outputs switch asynchronously and may briefly exceed the interrupt threshold. I'm not sure how to fix this. Most people design 74x148 without mask and sample unstable outputs. This can be fixed by holding 74x148 inputs stable during a read cycle by using 74x573. Or using the FPGA "double flop" technique. You may have to drop the comparator and mask each 74x148 input separately with eight OR gates.
The most unique part of your design is the ability to re-write instructions or data. You note that it is possible to re-write opcodes but I believe that it is much more powerful to re-write operands to handle awkward cases such as parity, Gray code or nybble swap. In your current design, you have four unused bits in your write-only interrupt priority latch and four unused address lines on the re-write ROM. While it may be tempting to synchronously set the interrupt priority and re-write pattern, interrupt may occur during the latch write instruction. This would leave your system in a completely mangled state. This can be averted with a latch write to ignore interrupts followed by NOP followed by latch write to begin re-writes. At this point, all operands must be pre-scrambled so that they pass through the ROM as intended. While it would be desirable for parity to be reduced to zero or one, this range of outputs would prevent the re-write latch in page $D0 from being addressed.
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