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Jmstein7
PostPosted: Thu Apr 07, 2022 12:57 pm 
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BigEd wrote:
Jmstein7 wrote:
... but then I read 265iromlist (cleaned up by Andrew Jacobs), which gives the code for the internal rom...

Do you have a link for this clean version? I did a quick search but it was inconclusive. Thanks!


Here you go: http://forum.6502.org/download/file.php?id=7788
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BigEd
PostPosted: Thu Apr 07, 2022 1:01 pm 
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Thanks!
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Jmstein7
PostPosted: Thu Apr 07, 2022 11:04 pm 
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BigEd wrote:
Thanks!


No problem! Hope all is well with you - it's been a while!
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BigEd
PostPosted: Fri Apr 08, 2022 6:50 am 
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Ha ha - all well thanks - holiday/vacation, friends, family, walking...
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Jmstein7
PostPosted: Mon Apr 11, 2022 6:08 pm 
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BigEd wrote:
Ha ha - all well thanks - holiday/vacation, friends, family, walking...


Okay, I've got it running at FCLK 6mhz with Port 3 at 115200 at boot. I'm still using the external clock for Timer 4. For some reason, I can't get FCLK over 6mhz. I just get garbage if I try.

Jonathan
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tokafondo
PostPosted: Mon Apr 11, 2022 11:49 pm 
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Jmstein7 wrote:
Okay, I've got it running at FCLK 6mhz with Port 3 at 115200 at boot. I'm still using the external clock for Timer 4. For some reason, I can't get FCLK over 6mhz. I just get garbage if I try.

Jonathan


I don't know how you managed to get Port 3 to run at 115200 at boot.

The ROM monitor listing has calculations for FCLK =< 6.144 Mhz, and bps =<57600.

Page 30 of the w65c265 datasheet v2.1 has the formula to get the values to program the timers for arbitrary FCLK and bps.
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Jmstein7
PostPosted: Tue Apr 12, 2022 1:39 pm 
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tokafondo wrote:

I don't know how you managed to get Port 3 to run at 115200 at boot.


Custom ROM.
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handyandy
PostPosted: Wed Apr 13, 2022 12:04 pm 
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Does your custom rom contain values for calculating FCLK over 6 mhz and corresponding baud rates?
The internal rom will default to 3.68 mhz on error.
BTW congrats!

Cheers, Andy
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Jmstein7
PostPosted: Wed Apr 13, 2022 2:20 pm 
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handyandy wrote:
Does your custom rom contain values for calculating FCLK over 6 mhz and corresponding baud rates?
The internal rom will default to 3.68 mhz on error.
BTW congrats!

Cheers, Andy


Andy,

Great question! My ROM doesn't need to do that because I made FCLK independent of the baud rate. I use TIN on P60 to connect an oscillator for Timer 4. In my case, 1.8432mhz. That is what it uses to set the baud rate. Therefore, you can use whatever FCLK you desire.

Jonathan
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Sheep64
PostPosted: Fri Apr 15, 2022 1:28 pm 
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I presume that you want to re-assemble the W65C265's monitor program but with UART not clashing. I understand that the monitor looks for a magic string at $8000 and then runs an external program. If you're not using the region from $8000-$DEFF, it might be quicker and easier to run a patched copy of the monitor from external ROM. It might also be desirable to use an external UART.

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Jmstein7
PostPosted: Sat Apr 16, 2022 7:50 pm 
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Sheep64 wrote:
I presume that you want to re-assemble the W65C265's monitor program but with UART not clashing. I understand that the monitor looks for a magic string at $8000 and then runs an external program. If you're not using the region from $8000-$DEFF, it might be quicker and easier to run a patched copy of the monitor from external ROM. It might also be desirable to use an external UART.


The "magic" bytes are "WDC", and the internal rom searches a few different addresses for that. But, I agree that an external UART is desirable.
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Jmstein7
PostPosted: Thu May 12, 2022 2:55 pm 
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Okay, here she is!
Attachment:
Image.jpeg
Image.jpeg [ 4.75 MiB | Viewed 512 times ]


I found two errors, but they were simple to fix with two wires and some solder.

Testing her like crazy!
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fachat
PostPosted: Thu May 12, 2022 6:06 pm 
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I would have hoped for a 65256 chip version that has lots of internal RAM and boots from SPI flash, so all IO pins would be available instead of having to sacrifice them for the system bus

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Jmstein7
PostPosted: Fri May 13, 2022 8:01 pm 
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fachat wrote:
I would have hoped for a 65256 chip version that has lots of internal RAM and boots from SPI flash, so all IO pins would be available instead of having to sacrifice them for the system bus

I guess that would have made too much sense (?)
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tokafondo
PostPosted: Mon May 16, 2022 10:00 pm 
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fachat wrote:
I would have hoped for a 65256 chip version that has lots of internal RAM and boots from SPI flash, so all IO pins would be available instead of having to sacrifice them for the system bus


Who knows... maybe some day WDC surprises all of us with a fpga based '265s, so what you say can be achieved.
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