I'm not too sure what version the end user will use (Rockwell most likely?) so I had to try and design that portion around them all. Hence the BE mistake.



I wanted to be able to use the AY3-8913 as a sound card expansion so I need 2 MHz on the bus but to maintain compatibility I had the bus stay on 8MHz and divided the clock speed on the sound card. As for the variable clock speed it can be useful to slow programs down and look for errors so I added that for debugging.



Looking at the datasheet now.



I have, it has been an interesting experience and all code has compiled. It's just under-developed and in need of a prototype (hard or soft) to fully test on.

Ah yes the 6551. I think it has been specially developed to talk to a modem - not like more modern use cases to talk to another rs232 endpoint via null-modem cable. So be aware about the behavior of the handshake lines if you intend to use them. Some work not really as you would expect for a null modem, like interrupting a byte in mid transfer. I'd also recommend another chip. I switched over to the 16550 due to its (potentially past) ubiquity and the fifo buffer - those allow buffering of high speed traffic while waiting for the CPU to serve the interrupt

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

Regarding clock generation. I was wondering why you use /q of the first register i.e. /4MHz as clock for the second. Not sure if that matters though. Did you draw a timing diagram.

I had a revelation when I saw the timing generator of the Commodore 8296 here left top http://www.zimmers.net/anonftp/pub/cbm/ ... 4-6of9.gif
Using a counter instead of several flip flops, you can use the output directly. Or like in the 8296, slice in a PROM to generate any kind of timing you need from the clock inputs, then qualify with 16MHz so all clocks have the transition at the same time and spurious signals when the PROM input changes do not bleed through

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

Btw did you check how many unused gates you have? I think I see quite a lot from the layout, although it's difficult to see traces on the back side.

I don't know kicad, but eagle has the tendency if you 'copy' a gate to quietly add a full IC. You have to 'apply' a gate so it shows you unused gates on existing ICs

Also just saw that your schematics also has duplicate inverters for address lines. If you suspect you will need an intermediate signal from one part, better name it and refer to it from another part.

Don't worry it usually takes multiple rounds of refactoring. On more complex boards I usually work multiple weeks with checking, optimizing, re-checking, re-evaluating features in multiple iterations before I get it to production.

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

May be a bit diffucult to find, it's in HTML so I would assume it has to be viewed in GitHub Pages here: https://thealmostgenius.geekgalaxy.com/WolfNet-6502-WBC/memory_map.html (Sorry about all the colour, I tried to make them as pastel as possible so it would be easier on everyone, no idea if it helped though.)



This will be added on a separate debug card with blinking (sorry, status) lights and 7 segment displays. (Like the ones you get in PCI for the x86 family.) Variable speed also helps to see the output in some cases where the speed is too quick to see, guess I could always log the output though.



That was my bad, I meant assembled but as I am writing this I am remembering that this means there could still be runtime errors.



Agreed, I have been whittling the schematic down to a stick from a branch, so to speak. This was originally going to be 90+ parts all built out of logic gates but I managed to strip it down to about 50 at the time of posting and my latest version is only 24 chips.

Cool! I'm sure you learned a lot!
Can you post the latest version?

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

As requested, the latest version.

If you want to save more chips I think you can combine some of the 138... u3 and u9 have the same inputs, same with u4 and u8.

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

Having examined your latest schematic (2.5), you should take a closer look at your I/O decode and chip selects for the various I/O devices.

You're using a pair of 74HCT138 chips to decode an I/O page of $D000, where the first one decodes the upper 4-bits to a "D" and the second one decodes the lower 4-bits to a "0". This works, but the outputs from the 74HCT138 decoders are active low. You're using a single 74HCT08 AND gate to obtain an active high signal for CS_DEV. This doesn't work as the AND gate requires both inputs to be active high to obtain an active high output. As you have multiple inverters leftover from the 74HCT04, you could use two of those to invert the output signals from the 74HCT138s driving the AND gate. This will result is a longer delay path due to the additional chips in the circuit.

Looking at the 65C22 used for GPIO, you have the CS1 and /CS2 lines reversed, i.e., the CS_DEV (which should be active high, goes to /CS2 and the CS_GPIO (which is active low) goes to CS1.

U4 and U10 are wired the same on input (as previously noted). The output selects start at $xx80 and increase by $xx10 to $xxF0. Note that $xx is $D0 based on CS_DEV.
- You show the UART I/O as $D014 - $D017, but the base select is $D090
- You show the 65SIB I/O as $D0C0 - $D0CF, but the base select is $D0A0

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Regards, KM
https://github.com/floobydust

Many thanks for all the help from everyone and any pointers/constructive criticisms. I have had a lot of ideas and help from you all.


Thanks floobydust, I noticed these issues too after I triple checked all the address decoding. This has been changed in the repository but I forgot to repost the schematics here. (Sorry everyone.) Changed the inputs and outputs on the 138s to reflect their true addresses and changed the CS_DEV AND gate to a NOR so that it goes HIGH when both signals are LOW. I believe the AND was left there from when the CS_DEV line was active LOW. Just goes to show that I shouldn't work without sleep.

U9 has two outputs that are combined with an AND. you can achieve the same result by removing A13 from the input, setting the input to low and then use the 138 output directly.
That leads to the question where A13 feeds into address selection. If I get it right A13 is not used, so you have 8k ROM pages, that are mirrored two times into a 16 address space.

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

Regarding the findings from floobydust, it helps to note the type of logic in the signal name. For example mark active low signals with a '/' prefix, or a N prefix or postfix. WDC notes them with a B postfix IIRC.
This way when you change the logic you either create separate signals and electrical rule check should warn you that a signal has no output, or if you rename a signal you can see the changed logic in the other places where it's used

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

since you're using Kicad you can also just name your active low labels/signals ~{name} which will put a negation line above them

also personally i always start by making my decoding circuit in a logic simulator to see if it even works, what gates it needs, and what could be optimized away.
especially when you're using discrete logic gates instead of something programmable, where mistakes are a bit more resilient.