In the RDY vs CLOCK STRETCHING thread http://forum.6502.org/viewtopic.php?f=4&t=5504

This is precisely the dilemma I'm facing in trying to design a *2MHz mod for the VIC20.

For the VIAs' timers and other operations that must occur at the established 1MHz rate I'll have to recreate, duplicate... emulate the 1MHz Ph2 the VIAs would normally get. (VIC schema calls it SØ2) That's relatively simple. I just have to invert the signal from the 6560 Vid controller that becomes the cpu's normal 1MHz and delay its falling edge.

My problem is conditions will be such that the Emulated SØ2 will rise around 50nS before the cpu clock that gets stretched will rise.

Currently, the difference is unavoidable because signals from the mapping/banking circuitry that will substitute RAM for the slow system ROMs won't be valid until 40nS after ESØ2 rises and I'm allowing 10nS of setup time to detect that condition.

So my question is will the 50nS difference between VIAs' (or any other 65xx I/O) 1MHz ESØ2 and stretched Ø0 have any deleterious affects on the VIA's normal internal workings when the cpu tries to access its registers? I'd like to think the answer is no but I don't want to take that for granted.

So far, my design amounts to 5-6 chips and seems a bit much for a measly 2X speed up. I've been trying to adapt Jeff's 74_163 solution to my plans but so far I've not had even a glimmer of inspiration. Bear in mind that if an I/O access occurs after a "2MHz" T1 the T2 that would normally follow would be suppressed and access would be deferred until the next cycle. So what I'd ideally have would be a Stretch or Wait hybrid. Ugh.

I am open to suggestions. Thanks.

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"I am endeavoring, ma'am, to create a mnemonic memory circuit... using stone knives and bearskins." -- Spock to Edith Keeler

I think there may be problems. The VIA requires that the address lines are stable at the rising edge of the clock phi2.

That is why it cannot be used in a C64 without delaying the leading edge of phi2.

Not sure here - the 2MHz CPU may already have the lines ready and stable. You may have to need the 2MHz variant of the VIA due to the shortened phi1

Edit: I think the 6522 is the only one where that A lines ready at rising phi2 applies, not sure about the riot 6532 and rriot 6530 though

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

Maybe if you can use a PAL/GAL you can use something like the 8296 timing generator http://www.zimmers.net/anonftp/pub/cbm/ ... 4-6of9.gif

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

The addresses would become valid 30nS after the 65C02's previous Ø0 In went low (tADS) , whether that clock had been a Long or Short T1 or a T2, so I don't see any problem in that respect. I guess my question needs clarification: Would the difference between ESØ2 and µC clock (when the latter is stretched) affect the 6522s' timer, counter or shifting operations? Would it matter to the 6522s, as long as my ESØ2 closely mimics the original SØ2 in frequency and durations? My optimistic self says no, all will be copacetic. My more dominant personality trait says, not so fast, Sparky.

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"I am endeavoring, ma'am, to create a mnemonic memory circuit... using stone knives and bearskins." -- Spock to Edith Keeler