I'm relatively new to 65816 assembly, and I'm wondering if I'm missing a simpler way to write to 8-bit registers on devices such as VIAs and PSGs. I have some code where the logic really benefits from the 16-bit accumulator. However, I need to write to a VIA and some PSGs which have 8-bit registers. I am switching my accumulator to 8-bit anytime that I write to these registers. Is this the proper approach, or is this some shortcut to STA, while using a 16-bit accumulator, that allows me to write a single byte and not two bytes? If writing two bytes, it updates the desired register plus the register at the next address. Thanks!

Okay, what about X and Y -- is it reasonable to keep those in 8-bit mode? They'd be fine for simple reads and writes to the 8-bit peripheral (but of course with X and Y you can't easily do AND OR EOR etc).

The other solution involves hardware. Just redefine the IO address decoding such that every other address is unused. For example, a 6522 VIA would occupy 32 (not 16) bytes of address space. Within the 32-byte space, all the even addresses would select the VIA, and all the odd addresses would select nothing.

This allows the CPU to do a 16-bit access while only touching the VIA once. On writes, the extra 8 bits get written to nowhere. But remember -- on reads, the extra 8 bits will contain undefined data, so your code will need to be on guard for that.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

That's a nice solution. And this is probably a bit crazy, but if you were feeling particularly adventurous you could wire up a second 6522 to cover the odd addresses. Between the two of them you'd then have 16-bit wide I/O ports. The timers and shift register wouldn't really extend so naturally though.

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Sorry, I should have included more info about X, Y. I would like to use 16-bit X and Y registers, as I'm indexing values above 255.

The addressing change is clever, and I think it would work well. I'll have to think about whether I can manage that with my current PCB design, or if I'll have to wait for a future version of my PCB before I can leverage it.

Thank you!

Very good points -- and something to which I am paying close attention. Thank you for the tips!

Although CPU A0 wouldn't connect to the peripheral's A0, it would connect to the chip-enable logic. As I said, all the odd addresses are unused, and would select nothing. This allows the CPU to do a 16-bit access while only touching the VIA once. The register would not appear at two adjacent locations, and there's no threat of a double access.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

It works with a single 6522 as well, PORTA is the high byte, PORTB is the low byte. This works for ORA/ORB and DDRA/DDRB. Timers also kind of work as expected (T1C, T1L, T2C) although there are some gotchas.

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