akohlbecker: I thought that it was extremely rude of me to mistakenly attribute your Digital diagrams to AndersNielsen and watch all of AndersNielsen's videos without watching your videos. After going through 20 hours of video, I feel exhausted. I expected to breeze through your videos in two days or so. However, it took me five days to watch the first 14 episodes due to the quantity of good information. You must be exhausted too. It must have taken you at least 200 hours to shoot and edit. Given that you've been working on these videos for more than one year, I'd be unsurprised if you spend an average of one hour per day working on video.
I feel vicariously productive after watching your videos and especially so after watching accelerated sections. I am reminded of W. C. Fields' quote "Work fascinates me. I can watch it for hours." More seriously, I knew that my work was a minimal hack but I vastly under-estimated the effort required to make a full system which conforms to data-sheet specifications.
My attention wavered more than usual in the first half of Episode 2, Episode 6 and Episode 14. However, I was amply rewarded in the second half of each episode. Likewise, I was riveted throughout Episode 15, Episode 16, Episode 17 (address decode), Episode 21 (6522) and your
series about two digit hexadecimal displays.
I wish that you had more split-screen video where the KiCAD schematic and the bread-boarding is updated simultaneously. Admittedly, keeping that synchronized would probably require more planning and would increase editing time. With the wisdom of hindsight, half KiCAD/half bread-board and half timing diagram/half data-sheet would be very desirable.
After you brought all 65816 address, data and control lines to one edge of one bread-board, I hoped that you'd make a short ROM, RAM and I/O bus extending in one direction while the address decode, interrupts and RDY logic would extend in the opposite direction.
The software which you use has been a moving target. For example, moving from KiCAD5 to KiCAD6 (although it looks like the KiCAD6 interface is borked in the same manner as GIMP). I appreciate that the style of your correctly scaled WaveDrom diagrams match your early manually drawn diagrams. Your early diagrams were preferable but it is probably quicker and more consistent to use the appropriate tool.
There has been some whinging about sound quality but it was only a faint milli-second echo and no worse than having a conversion in an empty room. From the complaints, I expected much worse. Concerns about power distribution were quite valid. Radical Brad prototypes up to 80MHz with a rectangular mesh of power and ground and places an oscillator in the middle. You had a tree of power distribution with an oscillator in the corner. However, this works due to fastidious use of de-coupling capacitors and short wires which are often color coded. Indeed, the exclusive use of red and black wires for power and ground is greatly appreciated.
There is a very minor error in the clock circuit which may cause very infrequent error. I have only learned this by reading all of
Advanced FPGA Design by Steve Kilts. A flop on the slow clock followed by a flop on the fast clock feels correct. However, it creates an obscure edge case. A "double flop" on the fast clock is more reliable. Either way, the slow clock has the jitter of the fast clock.
There is a re-newed interest in asymmetric clocks and you are well placed with this trend. I believe that your design currently has one spare, calibrated 10ns delay line. The delay line combined with one OR gate would create a high clock phase which is 20ns longer than the low phase. Save this for an episode of minor tweaks but it would be instructive to compare this against a uncalibrated bodge of three or four OR gates. Either arrangement would allow you to increase the maximum clock speed or operate with additional reliability.
I typically read text and watch video off-line. From bitter experience, I skim through the 6502 Forum to make sure that I haven't omitted any diagrams which are pertinent to discussion. During this process, I was uncharacteristically stopped by your address decode and I had to check that logic gates were used in multiples of four. ("Well, *that's* not accidental.") I am even more impressed by the optimization process which takes into account propagation delay and component availability. In particular, I am impressed by the speed at which you work. I say this after spending yet another 1.5 days on address decode.
Finally, no-one has mentioned the best feature of your design! Although you have fitted 512KB of extended RAM for demonstration, your design allows 4MB of contiguous RAM from $400000 to $7FFFFF and does not preclude significantly more RAM. In this regard alone, your implementation exceeds many people's vaporware.
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