To expand on that, according to the 1975 datasheet the Phi1Out and Phi2Out are non-overlapping, and reflect the clocks used within the chip. Mostly, 6502 output timings are relative to Phi1Out rising, and input timings (and the data bus as output) relative to Phi2 falling.
http://archive.6502.org/datasheets/mos_ ... g_1975.pdfAs BDD implies, whether it matters as to which clock you use will depend on whether the design is using an original NMOS 6502 or a modern CMOS 6502.
I suspect it will also depend on the behaviour of the RAM: in the 70s and 80s RAMs were rather slow. Modern RAMs are much faster. It might be that a bit of slosh in the circuit timing will be tolerated by the slower RAM, but the faster RAM will react, to bad effect.
You'd need a good scope and test program to investigate what the RAM is actually seeing.
So: which kind of 6502, and what speed of RAM, are two major questions when you have this kind of timing issue.