6502.org Forum  Projects  Code  Documents  Tools  Forum
It is currently Fri Nov 22, 2024 12:06 pm

All times are UTC




Post new topic Reply to topic  [ 5 posts ] 
Author Message
 Post subject: purpose of PH2O
PostPosted: Mon Mar 21, 2022 2:11 am 
Offline

Joined: Sat Mar 11, 2017 1:56 am
Posts: 276
Location: Lynden, WA
So a weird RAM corruption issue I was having turned out top be because, in my decoding logic, I was qualifying the r/w and oe lines with PH2O. When I switched to using the actual clock line for this, the system runs perfectly. Strangely, when looking at my rw and oe lines, compared to the true clock, things looked perfectly correct (oe and rw only happening on HIGH clocks, and edges looked pretty properly aligned to my eye). I guess I created a timing issue of some sort.

This incident leads me to a greater question. What is the purpose of the PH2O line? When would I want to use it? according to my scope, PH2 and PH2O are only out of phase by 5 nano seconds or so.


Top
 Profile  
Reply with quote  
 Post subject: Re: purpose of PH2O
PostPosted: Mon Mar 21, 2022 4:52 am 
Offline
User avatar

Joined: Thu May 28, 2009 9:46 pm
Posts: 8505
Location: Midwestern USA
Dan Moos wrote:
This incident leads me to a greater question. What is the purpose of the PH2O line? When would I want to use it? according to my scope, PH2 and PH2O are only out of phase by 5 nano seconds or so.

For a long time, most 6502 systems used a "roll your own" clock oscillator consisting of a crystal of the correct frequency and resonance type (parallel or series), along with the required passive components. Such an oscillator circuit is very limited in its fan-out capability, plus it can only produce one clock signal phase. The PH1O and PH2O outputs were provided to produce a more robust clock, as well as two signals that are 180 degrees out of phase. At the relatively sedate speeds at which the NMOS processors ran, the lag from PHI2I to PH1O and PH2O was of no consequence. That lag became a problem with the CMOS processors as the clock speed was ramped up.

WDC discourages the use of PH1O and PH2O in new designs for several reasons, one being the aforementioned lag—it is not a controlled feature, is not production-tested and is unspecified. Furthermore, the phase relationship between PH1O and PH2O, while nominally 180 degrees, is not guaranteed. As the data sheet says on page 26:

    PHI1O and PHI2O clock delay from PHI2 is no longer specified or tested and WDC recommends using an oscillator for system time base and PHI2 processor input clock.

PHI1O and PHI2O are retained for use in cases where the 65C02 is replacing a 6502.

For a robust clock, you should use an HCMOS “can” oscillator and run its output through a flip-flop, 74AC74 or 74AHC74 recommended. Naturally, use of the flop will result in a Ø2 frequency that is one-half the oscillator's. An alternative if you also need wait-stating to accommodate slow devices is to use a 74AC163 counter instead of the flop, such as illustrated here. See Jeff's write-up for circuit details.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!


Top
 Profile  
Reply with quote  
 Post subject: Re: purpose of PH2O
PostPosted: Mon Mar 21, 2022 7:27 am 
Offline
User avatar

Joined: Thu Dec 11, 2008 1:28 pm
Posts: 10985
Location: England
To expand on that, according to the 1975 datasheet the Phi1Out and Phi2Out are non-overlapping, and reflect the clocks used within the chip. Mostly, 6502 output timings are relative to Phi1Out rising, and input timings (and the data bus as output) relative to Phi2 falling.
http://archive.6502.org/datasheets/mos_ ... g_1975.pdf

As BDD implies, whether it matters as to which clock you use will depend on whether the design is using an original NMOS 6502 or a modern CMOS 6502.

I suspect it will also depend on the behaviour of the RAM: in the 70s and 80s RAMs were rather slow. Modern RAMs are much faster. It might be that a bit of slosh in the circuit timing will be tolerated by the slower RAM, but the faster RAM will react, to bad effect.

You'd need a good scope and test program to investigate what the RAM is actually seeing.

So: which kind of 6502, and what speed of RAM, are two major questions when you have this kind of timing issue.


Top
 Profile  
Reply with quote  
 Post subject: Re: purpose of PH2O
PostPosted: Mon Mar 21, 2022 5:32 pm 
Offline

Joined: Sat Jan 02, 2016 10:22 am
Posts: 197
Would PHI1O and PHI2O be part of the 6501 / 6800 socket compatibility legacy ?


Top
 Profile  
Reply with quote  
 Post subject: Re: purpose of PH2O
PostPosted: Mon Mar 21, 2022 5:37 pm 
Offline
User avatar

Joined: Thu Dec 11, 2008 1:28 pm
Posts: 10985
Location: England
Yes, I think it's related. If you look at the block diagram in the '75 datasheet I linked, you'll see that the single clock in is fed to a clock generator and the two derived clocks are used and also exported. It's the bringing on-chip of the clock generator which was a major step forward for the 6502, and the earlier systems would have had those two clocks available as references.


Top
 Profile  
Reply with quote  
Display posts from previous:  Sort by  
Post new topic Reply to topic  [ 5 posts ] 

All times are UTC


Who is online

Users browsing this forum: No registered users and 10 guests


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to: