> It looks like the inverter for brk6_latch1 is missing.

Ah, I get it, as a result of the optimization everything is fine there, sorry

_________________
6502 addict

org, nice going.


To the readers of this thread:
The situation is, that we have two teams which had used different approaches, notations and logic symbols for dissecting a CPU core.
//Assuming that the 6502 core and the 6509 core are identical at logic design level.
So it is fully normal to have false positives when cross_checking the results of both teams for errors.

For instance, I'm an old school hardware guy with absolutely no LogiSim experience,
and to me it wasn't obvious that a transparent latch like 74373 could have an inverted and a non_inverted output,
what had confused me a bit, sorry.

Also, in my schematics the disabling of the PLA product terms 92:T2.ANY_ABS, 99:T3.ANY_ABS, 145:Tx.IMPL
happens inside the PLA, while the 'org' schematics had moved that part into the random logic area,
what had confused me a bit, too.

So please see them false positives as a proof that we are just trying to do a good job while cross_checking the results.

I did a little work on the Data Path diagram at the bottom.

- Missing S and ADL connection (S/ADL)
- The fact of loading direct and inverse value to the BI ALU latch is not reflected (DB/ADD, NDB/ADD)
- Zero load command is not displayed on the AI latch (0/ADD)
- ADL/ADD connects ADL and BI (not AI)
- Current value refresh commands are not displayed (S/S, PCL/PCL, PCH/PCH)
- Instead of "BCD-detect" made ADD (Adder Hold) and output to ADL and SB buses from it
- A -> AC (not to be confused with A Input)

_________________
6502 addict

In addition to the previous post.

- CGH and CGL are mixed up
- Adding a cleaner version of the diagram

_________________
6502 addict

I admit that I was in a hurry when drawing the block diagram with the bus systems,
it was the last step of the dissection.

It isn't exactly a data path diagram, because it shows the data path plus the address path.
Block diagram intentionally was kept as simply as possible to give an overview.
Don't worry, I'm adding a more detailed version.


My mistake, fixed.


I consider the AI and BI latches (plus the related circuitry) to be integral part of the ALU.


My mistake, fixed.


I consider the refresh paths to be integral part of the registers.


I consider the 'adder hold register' to be integral part of the ALU.



In Hanson's block diagram, the accumulator is labeled 'AC', so I'm changing 'A' to 'AC'.


Dang. How could this happen ?
My mistake, fixed.

Small case SB_S:

For some reason, the 6-nor is split into two gates (in the demorganized version 4or + 2or).

I am attaching the transistor circuit and a piece of dissection to get the #SB/S.

_________________
6502 addict

Case SBXY:

On the transistor circuit, the SBXY intermediate signal (SB>X,Y) comes in only one place - ZTST.

_________________
6502 addict

Reason was, that there were no 6or or 8or logic gates in the libraries of the CAD software I'm using.


Ah, that... maybe I had skipped a step during optimisation:


0)
org:ZTST = SB>A | AND,BIT | SB>X,Y | org:T6
the output of an AND gate goes into the "SB<>DB# NOR": NOT(AND,BIT) & org:ZTST

1)
so we could consider that input of the "SB<>DB# NOR" fed by the AND
to be the equivalent of the output of a three input OR gate:
SB>A | SB>X,Y | org:T6

2)
So I had pushed that three input OR gate into the "SB<>DB# NOR gate".

Cosmetic case DSA#:

I noticed that DSA# is obtained in random logic, but is not mentioned in the command block.
We know where it comes from, but for example, who will study it, will not immediately notice it.

_________________
6502 addict

Good point,
so I added 6 signals to that part of my schematic:

0>ADL0, 0>ADL1, 0>ADL2,
DSA#, 0>ADH8, AVR.



BTW: could you please label the output signals of "Pattern Readout" and "V. Inversion"
in the silicon pictures of the NES PPU ?

Done If there is anything else, you can safely go through the Issues section: https://github.com/emu-russia/breaks/issues

_________________
6502 addict

Thanks.

Case BCD_Carry:

To calculate DC3, AND0 and OR0 are mixed up.

I even did a unit test to see if there was an error.

This is the last circuit that completes the series of checks between your circuits and ours. I can say that our schematics had a lot more errors and this comparison helped us a lot. Great work, thank you!

_________________
6502 addict

Woot: eventually a nice electrical error in my schematics.
Error confirmed and fixed, thanks.

There are two possible ways of implementing a carry chain,
and it looks like I had mixed something up by accident.



;---

Also, in my schematics the ALU input carry sometimes was labeled 'ALU_cin#' instead of 'Ci0#'.
Fixed that to make things more consistent.

;---


Thanks for the appreciation and the kind words.
You and your team also did a great work with that 6502 dissection:
not many people out there would have been able to do something like this.
6502 core is a very compact, very tricky beast.

This comparison has helped the whole community a lot:
We now have schematics of the 6502 core in optimized (demorganzied) form and in not_optimized form,
also we were able to identify all of the functional blocks within the control circuitry.
It should be possible now for the community to figure out, what exactly happens inside a 6502 core, and why.

For supporting "breaking NES book, 6502 core",
I'm posting my big 6509 schematic broken into smaller pieces,
with signal and flipflop names changed according to that book.


Дава́й.