Hi all, newcomer here.
It seems to be CPLD experience on this forum, and I could need some help. I am working on the refining an old 8-bit system using a ATF1504, WinCupl, ATMISP and ATDH1150USB for JTAG programming. The CPLD works fine for chip select and other logic. 4MHz clock speed.

I plan to substitute a 74HC540 used as a keypad interface. One of the keypad switches/data lines should be like this in the CUPL code:



Resulting fit file contents looks fine:


However, it does not work, the uP does not get any key input as it does with the 540 in place.
Have I misunderstood anything obvious here? Maybe timing issues? Any tips are welcome.


Thanks in advance and all the best,
Tore B
Oslo, Norway

74HC540 internals:

Welcome! I don't see any obvious mistake - but it's easy to miss the obvious...

Perhaps double-check your pin assignments - perhaps even check the logical behaviour with 0V and 5V inputs.

But if it's not a logical error, then a timing error seems possible.

Or maybe there are other ways, preferred ways, to describe three-state outputs and negative logic inputs?

BigEd, thank you for your prompt and welcoming answer.
Using CPLD's has indeed had a steep learning curve. I have struggled with this for several days now, pins are OK. I let the compiler choose pins, and have triple-checked the connections.
I have tried using a different variant of CUPL code like this:
PINNODE = KEYLATCH_1;
KEYLATCH_1 = !KEY1;
AD0 = KEYLATCH_1;
KEYLATCH_1.OE = !GATE1 & !GATE2;

However, this does not work either, the resulting fit file output is the same as above, so the complier obviously simplifies the equation.
I have seen some WinCupl bugs regarding capital/lower case letters using flip-flops/latches, but using .oe instead of .OE does not change things.

I am still working on this, I will try to smoothe the gating signals with 68 ohm series resistors.

Cheers,
Tore

SOLVED!
A ringing filter with a 68ohm serial resistor on smoothed the high-frequency gating signal (OE signal) did the trick.
I am a beginner with CPLD's, and after reading other threads on this forum I ended up with the speed- and visibility optimized code below.
All the best,
Tore

Excellent!

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Thank for all input. I have added the output_fast = off after input in other threads in this forum.

Now, my next challenge is that I want to substitute a second 540 IC.
Could the above construction be expanded so I can have a second set of buried latches, connecting to the same address bus lines, but with different output enable triggering signals? My first code attempt returns errors that all AD lines already are assigned when defining the second buried latch output connection.

One solution could be to define some sort of CPLD-internal address bus that several latches can connect to.
Or maybe I could use only one latch, and define logic to select the latch input sources?
Any tips?
Thanks in advance,
Tore

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Thank you for taking the time to answer me.
I am sorry for my confusion in this, my eyes are sore from trying to understand the CUPL example files and PDF documentation.

The 74HC540 is a tri-state buffer, (indeed not a latch) and my original 8-bit computer design has two of these connected to the address/data bus. They have individual enable logic, and the CPU is reading their 8-bit values in turn, as keypad and general input ports. The 540 remain in high impedance state until both gate inputs are low.

My goal is to implement this in a ATF1504, routing the two input ports to the ATF, as well as the address bus as birectional port.
The internal 540-implementation should feed the AD bus with the port inputs, and I would also like to use the AD bus internally for some other CE logic as well.
I thought this could be achieved by using the .OE function, but I am truly a beginner in the use of CPLD's.

Thanks in advance,
Tore

I'll deal with the dual-540 setup later.
I now have to find out how to use bi-directional pins in the CPLD. There's a hint in the CUPL manual, but it refers to a application manual that is not available to me.
I have already routed the AD bus to the CPLD and successfully implemented a '573 external address latch, producing the A0-7 part of the address bus.
However, I also need to interface this bus with the above mentioned keypad signals, and thus need to program this in a bi-directional fashion. I have read somewhere that bi-directional pins needs to be read using the .IO extension, and any output must be done by the use of the .oe extension.

Would the above be the correct definition of the bi-directional AD bus here? (.io used in latch input and .oe use din the key value output?
I need to use this bus as input to other logic functions as well in the CPLD. I guess I can do this, but also need to use the .io extension in these statements?

Thanks in advance and cheers from,
Tore

Have you had a look at the Atmel example file ATF8255. I had a quick glance, there's a lot of code in there but it may have the answer you need.

Martin, thanks.
I have indeed been trying to understand this file, but it has a very high complexity, at least to me. I am having problems to extract the bidirectional pin read/write technique from the rest of rather complex logic.
I am in the process of trying the above code, it compiles OK, and it looks like it works. Nothing would be better...
Cheers,
Tore

Daryl’s 65SPI is written in CUPL. It is fairly complex with internal registers and multiplexed output data bus. I’m not proficient in CUPL, but know enough to convert it to Altera schematic. As an example code, you may want to take a look at Daryl’s CUPL design file and my equivalent schematic.

viewtopic.php?f=4&t=1265&hilit=65spi&start=75#p81413

https://sbc.rictor.org/65spi2.html
Bill