This is a RAM diagnostic that first checks the zero page and stack ($0-$1FF) without using any RAM resources. Once ZP and stack tests passed, it uses ZP and stack to run full RAM test from $200-$DFFF. RAM test is attached. The hardware has successfully passed RAM diagnostic at 7.37MHz.


Since all active components are populated, I'm trying higher frequency system clock to find out the design margin. The RAM test will run OK with 11MHz oscillator, but won't sign on with 14.7MHz oscillator, even with faster EPROM (W27C512-45Z 45nS). Adding one wait state to EPROM access allows it to run test up to 18.4MHz. At 22MHz EPROM is able to boot and test RAM but zero page and stack test failed. I'm happy with the design margin. I think faster RAM should allow it to run in high 20MHz speed.

In next session I will add a serial receiver and a basic monitor making this board into a functioning 6502 single board computer.

Serial transmitter is a pretty simple circuit. It is basically a parallel-in, serial out TTL 74165 shift register with some circuitry in the front end to handle the START bit. Serial receiver, on the other hand, is more complicated. The backbone of the receiver is a serial-in, parallel-out shift register, but there are complicated control circuit that detects the first high-to-low transition (START bit), sample the transition mid-bit to make sure it is not noise, capture data mid-bit, shift data 8 times to receive the data, latch the received data into a hold register, and generate a "receiver ready" flag.

The receiver schematic is below. The top row of registers are the shift registers for incoming data and STOP bit. The SRFF below the shift register detect the first high-to-low transition and start the receiver state machine. The state machine is two cascaded 4-bit counters; the counters are running 16X the receiver baud clock; the first 4-bit counter samples data mid-bit and enable the 2nd 4-bit counter; the 2nd counter counts the number of bits received and stop and reset when 11 bits are received. At the end of receiving a byte, the RxRDY flip flop (lower right) is set. There are 20 macrocells in this circuit. It is somewhat complicated, and it is reasonable to consider whether design in Verilog may be easier to understand. Sadly, as I retired and became older, I seem to have forgotten Verilog, regressed to my TTL days and found schematic easier to understand.


So not to muddy up the core receiver design, I turn it into a symbol and added a hold register and status register outside of the core receiver symbol. Adding decoding logic for the receiver, transmitter, status and data path for input/output of the serial port, the design starts to look cluttered. This is a good point to think about hierarchical design to reduce the clutter. I have not talked about CPLD macrocell utilization because it is low up to this point. With serial port added, the macrocell utilization is now 92 macrocells or 72% of the 128 available macrocells.


As a quick test of this receiver, I modified the previous memory diagnostic test to wait for console input between each test.


The transmitter can be improved with Transmit Empty flag, but that'll wait for another day. Next time I'll work on a usable monitor instead
Bill
edit: fixed the "16-bit" counters to "4-bit" counters.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

The purpose of the CPLD + 6502 trainer is to show the flexibility of CPLD and how it can first test a microprocessor (6502 in this case) and then assist it with various functions. My intention is not to build a full-feature peripheral, but instead providing sufficient functionalities of many peripherals that makes up a functioning microprocessor system. The great strength of CPLD is its programmability, so as the needs of this "functioning microprocessor system" evolved or repurposed to different applications, CPLD can be reprogrammed to suit the evolving requirements. Beside having 7-segment display and a functioning serial port, I hope to show in subsequent sessions SPI, I2C, PS2 keyboard, EPROM programmer, LCD display, WS2812B driver, W65C816 option, and even a free-standing graphic controller with the help of CPLD. I'm sure I'll think of more functions as I go along. These functions will not all exist in one CPLD instantiation nor will they be full featured, but they will be sufficiently capable to demonstrate a subset of the stated functions. Stay tuned, I've just started.
Bill

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Below is screen capture of a simple monitor for the 6502 SBC and source file attached. This monitor has the four basic functions of load file, display memory, modify memory, and run program. I also added the memory diagnostic routine from the previous session. It is not much, but has sufficient functions to load and run better programs.



The CPLD+6502 trainer is now a functioning 6502 SBC. The nominal clock is 7.37MHz. It does run at 14.7MHz as is. With faster SRAM and 1 wait state EPROM I am able to run it at 25.175MHz which will be useful for an application later. Right now it will stay at 7.37MHz. I soldered in rest of the connectors and put it in a PacTec CM5-125 enclosure. This is wrap up the development phase of the CPLD+6502 Trainer. I have a number of applications for it, but I'm taking a short break to tackle other projects.
Bill

Thanks again Bill, looking forward to reviewing the various stages in hardware and looking to the future developments. At some point could you post a bill of materials etc. as per your usual practice on your retrobrew computers pages?
Larry

Home page for rev0 of CPLD6502 Trainer is here. This is where design information (schematic, CPLD design, gerber photoplots) and software will be stored. There is a list of the various training sessions at the bottom of the homepage. --Bill
https://www.retrobrewcomputers.org/doku ... cpld6502r0

While moving a SST39SF010 flash from TL866 programmer to CPLD6502 trainer, I inadvertently inserted the chip backward and damaged the flash. This incident makes me think about an in-situ flash programmer as the first project of CPLD6502. In-situ programming means the flash can be reprogrammed without removing from its socket; furthermore, a blank flash can be programmed from scratch. This is not meant to be a general purpose flash programmer. I just want it to program the inexpensive Microchip SST39SF0x0.

The features of an in-situ flash programmer are:
* Two modes of operation, program mode and normal mode,
* Bootstrap from an internal CPLD ROM in program mode,
* Load data to be programmed and associated algorithm externally,
* Able to write to flash's command registers to execute program command sequence
* Boot from freshly programmed flash in normal mode.

This will be a mult-session project. In this session I'll talk about the theory of operation as implemented in CPLD6502 trainer. Next session I'll describe the CPLD design and ROM bootstrap program; the last session is on program loader, flash algorithm and data to be programmed.

Theory of operation of an in-situ flash programmer as implemented in CPLD6502 trainer.
There will be two modes of operation. In normal mode, the CPLD6502 boots off the external flash located at $F000-$FFFF; in program mode, the CPLD6502 boots off an internal CPLD ROM located at $F000-$FFFF while the external flash is a write-only device write accessible from $8000-$FFFF. Power cycling or reset is the only way to enter normal or program mode. No operator interaction needed (other than turn on the power) to boot in normal mode. To boot in program mode, the switch labelled "Single Step" need to be pressed and hold while power is applied.

The memory map of normal mode is as follow:
$F000-$FFFF, external flash read only.
$E000-$EFFF, I/O space, internal serial port is located at $E400-$E4FF
$0000-$DFFF, RAM, read and write.

The memory map of programming mode is as follow:
$F000-$FFFF, internal CPLD ROM, read only
$E000-$EFFF, I/O space, internal serial port is located at $E400-$EFFF
$0000-$DFFF, RAM, read and write
Write access to $8000-$FFFF will shadow write to the external flash. The external flash is not read accessible.

The reason for shadow write of the external flash is because programming command sequence requires write access to registers at address x101 0101 0101 0101 and address 1010 1010 1010 1010. This corresponds to addresses $D555 and $AAAA. Higher order address bits are ignored. This is a common protocol for programming flash memories. Since flash is shadowed from $8000-$FFFF, up to 32K of flash can be programmed. However because the normal mode only uses 4K of flash from $F000-$FFFF, this programmer will only write top 4K of flash.



The block diagram above shows how mode influences the data path and controls of flash memory. Mode input is latched at the rising edge of nRESET. Mode latched low is the program mode that enables ROM data path in memory space $F000-$FFFF. Program mode also disables the active-low flash output enable. It also disables the active-low flash chip select unless it is a write to $8000-$FFFF.

If mode input is latched high, it is in normal mode where internal data path is disconnected from the ROM; the active-low flash output enable is always enabled; the active-low flash write enable is disabled, and the active-low flash chip select is enabled when reading memory area $F000-$FFFF.

In next session I'll describe the boot ROM and how the concept is implemented in CPLD.

Bill

Part 2 of in-situ flash programmer describes the small boot ROM in CPLD, implementation in CPLD and required engineering change.

Once the programming mode is enabled, the external flash memory is disabled and 6502 will boot from the small ROM in CPLD. This ROM is a small lookup table so not to take up too much of the limited CPLD resources. Below is the bootstrap ROM assembly source:


This small CPLD ROM program puts out a prompt and copies 256 bytes of data from serial port to RAM starting from $200-$2FF and then jump to $200. The 256-byte program is an Intel Hex file loader which, in turn, loads flash programming algorithm and the data to be programmed. This is the small CPLD ROM program as a lookup table in Verilog:


Attached is the schematic of CPLD. The mode latching logic, ROM data path, and external flash memory controls are similar to the block diagram described in Part 1. The external flash memory requires independent chip_select, output_enable and write_enable control signals. In current board design flash memory's chip_select and output_enable are tied together. So it is necessary to cut the trace between flash chip_select and output_enable and connect a spare output to flash output_enable. See "Cut D" and "Jumper D" of the attached picture.

I compiled and programmed the CPLD; verified it will boot from external flash in normal mode and when "Single Step" button is depressed while powering up, the console will receive a "<" prompt indicating the serial port is waiting for input. So it is ready for Part 3, loading of flash programming algorithm and data.

(BTW, it was not as simple and straightforward as the above paragraph implied--there were quite a bit of design iterations and "sailor talks" before I can write the last prargraph.)
Bill

I developed a ROM emulator which uses a Teensy and can be programmed in C via the Arduino IDE which could be useful for your project.

https://microcorelabs.wordpress.com/202 ... -emulator/

Very nice ROM emulator! I like the idea of emulators or added functions in form of 32-pin DIP or 40-pin DIP.

In this particular case the CPLD is flexible and has spare capacity so diagnostic function and/or test points can be easily added to solve a specific problem during hardware development. During ROM code development I will use scripting tool like TeraTerm Macro commands to automate file loading and flash programming so I expect the flash can be reprogrammed under 10 seconds.
Bill

Part 3 of in-situ flash programmer describes the Intel Hex loader needed to load subsequent programs, algorithm for programming SST39SF0x0 and the data file.

Once the flash programmer has booted into programming mode (hold down "Single Step" button while apply power), it outputs a '<' prompt and waits for 256 bytes of binary data from the serial port. Attached is the Intel Hex loader sent to the flash programmer. This 256-byte file loader recognizes Intel Hex file and the "Gxxxx" (run from location xxxx) command. The file loader puts out a "X->" prompt when it starts up. Now I can send one or more programs and execute it. The first program is the memory diagnostic to check out the hardware as described in previous session (attached).




Now the Intel Hex loader and hardware memory are checked out, lets load the SST flash programmer attached below. The SST programmer expects a data file to be loaded in RAM from $7000-$7FFF which will be copied to $F000-$FFFF. The program implements the "Sector Erase" and "Byte Program" algorithm for SST39SF0x0. Since the flash is accessible only as write-only device, the SST program is not able to read the device's status by polling data bit7,so it just waits for the maximum specified time for erase and programming to complete; sector erase time is 25mS, max; byte program time is 20uS, max. Only sector $F000-$FFFF is erased and byte-programmed so the programming operation will complete quickly.



The data file is the CPLD6502 monitor described previously (attached). It resides in flash at $F000-$FFFF but its hex file is relocated to $7000-$7FFF to be loaded in RAM at $7000-$7FFF then copied to flash at $F000-$FFFF. This is the screen shot of the programming session followed by booting the flash that was just programmed.



A TeraTerm macro file to load Intel Hex loader, load SST algorithm, load data file, and program the flash is also attached. It took only few seconds to execute.


This demonstrated the flash programmer is functional and completed the project.
Bill

Atmel ATF1508AS vs Altera EPM7128S

EPM7128S is the heart of CPLD6502 trainer but it is obsolete even though it is still possible to acquire them in the secondary markets. Atmel ATF1508AS is currently in production and is the replacement with the same pin assignments and logic organization. However, ATF1508AS is more expensive, requiring a different and more expensive programmer, and using a buggy WinCUPL tool. Instead of designing with WinCUPL, it is possible to design in Quartus, convert to Atmel equivalent with POF2JED, and program with Atmel programmer. This translation process is not problem-free. In the past, specifically with 64-macrocell EPM7064S, I've had success translating simpler designs to Atmel's equivalent, ATF1504AS, but the translation failed with more complex designs. I want to try again with translation of EPM7128S to ATF1508AS, so I bought and received 3 ATF1508AS ($11 each) from Mouser. The ATDH1150USB programmer is even more expensive now at $73, but I already has purchased one.

Despite Atmel's documentation, ATDH1150USB programmer does not work with my lab computer which is Windows Vista but does work with Windows 10. The POF2JED software is easy to use and the ATMISP programming software is also reasonably easy to use. I went back to the earlier CPLD6502 designs and translate them to Atmel programming files with POF2JED. Then program Atmel ATF1508AS with ATMISP.



I've converted 6 CPLD6502 designs and verified ATF1508AS has the same functionalities as EPM7128S. So far ATF1508AS appears to be a viable alternative to the obsolete EPM7128S but I do notice significant higher current consumption as the complexity increases. Here are 4 current measurement of designs on CPLD6502 in order of increasing complexity:



Personally I will stay with EPM7128S until my stock run out.
Bill

I quite like this topic. It reminds me of NAND2Tetris because each step is sufficient for independent exploration. Want UART with parity? Add that yourself.

I've seen quite a few schemes where a memory map is re-arranged for flash programming. In this case, it is not required. The CPLD may selectively source reads from itself or flash storage. All writes may be directed to flash storage without restriction. Unless the magic knock sequence occurs, all writes will be ignored. Instruction fetch (or vector fetch) from flash would disrupt the knock sequence. However, if reads are exclusively from CPLD or RAM then writes to flash are not disrupted.

The current measurements for Atmel ATF1508AS are horrendous. I knew that the minimum was 105mA but I had no idea that 247mA was possible. Actually, 247mA * 5V = 1.235W. You're gonna need a heatsink on that. There might be variants which automatically fall into a low power state. I think they have a Q or Z suffix. However, they don't wake on a time-scale which is useful for address decode.

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