Hi guys

Can anyone who has experience designing for the 65816 know the realistic maximum number of devics (TTL/CMOS load) you can have being driven by the address bus and various control signals such as RWB? (data bus wise, it would be down to the buffer/PLD (in my case the ATF1508).

In my upcoming design I've possibly gone a bit overboard (using Kicad so more PCB room!) with : 4x VIAs, 1x SC28L92 (serial), 2xSRAM ICs, 4 Flash ROM ICs (one is the OSROM, 3 paged ROMs), 3 PCI-type edge connector slots (the PCI slots have address, data bus, RESB, NMIB, RWB, PHI2, PHI1, amongst other signals)
I'm thinking I might have to buffer the PCI slots given they go offboard and I plan to implement a graphics card using one of them.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

I hope your upcoming design uses an '816 that's in a PLCC or Quad-pack package -- not a 40-pin DIP. That's because driving the capacitance of a heavily-populated bus results in substantial current spikes in the Gnd and Vcc pins of the CPU. It's to your advantage if (as with PLCC and Flat-pack) there are multiple Gnd pins and multiple Vcc pins to help carry these spikes without creating too much of a voltage drop.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Thanks for your replies and that all sounds positive. I just need to see if the ATF1508 behaves under such load. My suspicon is yes, but we'll see. I also forgot to include the RTC DIP IC.

Jeff: I can certainly move the 65816 across to PLCC (currently DIP), but I was hoping to avoid it as I have begun hating routing PLCC , but on balance I'd rather do the routing and it actually work.

With the rest of the devices (if it matters at all): Due to programmer constraints (the PLCC adapters (scroll dopwn) are £100+ a pop) I'm having to stick with DIP for the OS & paged flash roms. Also the two SRAM ICs & RTC are DIP as those are what I have 'in stock'. Total: 8 devices.
PLCC-wise: The SC28L92 and the VIAs are all PLCC: 5 devices. Will add the 65816 to that as well as you recommend.

That should be alright. The CPU is the chip that's most critical because it has far more output pins to drive. (At the start of every cycle, all 16 address lines may simultaneously change, and all the "data" bus pins, too, since they output the Bank Address at this time. Also we have RWB and some others that may change.)

I wouldn't worry about buffering, but I'd strongly recommend you make provision for series termination -- definitely for the Phi2 signal, and preferably for all the other signals, too.

By "make provision for" I mean providing a site where a resistor or resistor array can be installed, in a socket, perhaps. You can start with zero ohms or some other negligible value. But probably your 'scope will reveal less ringing if you up the value to 50 or 100 ohms (the best value to be determined by experimentation).

Series termination means the resistor will appear at the source end -- on the motherboard, not on the plug-in card that receives the signals. Hopefully you'll post a proposed schematic, and we can deal with the details then.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

The design is spread out amongst a ton of Kicad sheets. I usually do the all-in-one page approach, but the consensus seems against that from what I've read online. This means I can't just post one schematic, but I'll get what I have so far posted a bit later. Just keep in mind it's not competed, particularly the glue logic as I need to finish the design of the CPLD logic, let it assign most of the non-clock pins and then reflect that in the schematic.

BDD recommended a while back putting a 100-200 (ish) ohm resistor as close to the PHI1 and PHI2 D-flipflops as possible to deal with ringing. I think this is what you're referring to with regards terminating? So it goes: oscillator > d-flipflop > resistor as close to output as possible > the rest of the circuit.
If this is the case then I'd probably put resistor networks (in-line, not bussed to VCC) on all address bus and data bus pins in the same manner. I know you said it really only affects the MPU, but would the ATF1508 CPLD possibly suffer from this as well given that it pretty much deals with all device selects, IRQs, NMIs, produces WD & RD, inverts RESB, and latches out the data bus?

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Not entirely sure. I think it was when I was watching a batch of Kicad videos (so more watched/listened than read) a while back.
I agree with you, but as I'm a hobbyist (at best!) I thought that was just me so was going with the *seeming* proper method.

Here are the schematics. I've not included the VIAs or the glue logic CPLD because they aren't finished (the CPLD exists as a device on the sheet as I'm still working on the PLD/JED design so the pinout is not finalised). If you don't want to look through this lot then let me know and I'll put them all on one sheet.

Note that the Flash ROMs and RTC are 70ns parts so will be accessed with PHI2 stretched, where-as the other devices (includng the VIAs) will be accessed at full speed. The VIAs will be hooked up to the GC (global clock) rather than PHI2 to prevent slow down on their internal counters. Click stretching is determined by the CPLD uisng the /WSE signal.

Final note: The design isn't at all finished and something are likely to change. The clock generation, mpu/ram/rom/rtc/pci slows are mostly set, but power, serial (mostly the GPI and GPO pin usage) VIA ouput ports and CPLD glue logic are still under consideration.

Core MPU, OSROM, RAM, RTC:
Clock Generation:
Core signals:
PCI bus I/O:
Power:
Serial:

Yes, in-line. IOW, in series. There is also such a thing as parallel termination, where a node gets attached to the junction between a resistor to ground and a resistor to Vcc. I won't try to say why that's more appropriate in some situations and less so in others. But series termination is easy and can help a lot, and that's why I suggest it.

Locate the resistor reasonably close to the signal source, be it the CPU, a flip flop, or whatever. And 100-200 (ish) ohms sounds high to me, although it'll depend on circumstances. I'd be more inclined to start with 50 ohms or so. If you socket the resistor arrays then you can try different values and see how things look on the scope.

It's somewhat of a judgment call. More ohms is gonna give a visually smoother waveform, but it also increases delay. So you don't wanna go overboard making it look all soft and pretty. For clock lines, at least, you wanna keep the edges crisp, even at the expense of a small amount (say 0.5V p-p) of residual ringing.

If its outputs have very abrupt rise and fall times like those of WDC CPU's then yes.

I see you've posted some schematics while I was typing. Will have a look at those later...

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Definitely. I set up a breadboard to test the delay circuit we were discussing a while ago and as part of that I also added in some resistors (one leg cut super short on the flipflop side) and compared with and without. Obviously not the same as an entire single board PCB, but I did see a big difference in ringing which is what really sold me on it (there's nothing like seeing something actually working in front of you). As such, definitely going to be included, but I will experiment with values and see what happens.

With regards pull ups:
I've got plans to add 2K2 pull up resistor networks for the ATF1508 CPLD. If I need them I can fit them, if not - I wont . Interestingly, my existing 6502GPD rev B design doesn't have pulls up and I can see that the digital highs are at TTL voltage level. So far haven't seen any issues apart from the design won't push past 12MHz (discussed in another thread and I'm still looking into it).
Maybe not such a great surprise as the design has the usual WD65C02S CPU & WD65C22S VIAs along with AS6C4008 for RAM, Winbond W27512 EEPROM - all of which are noted as being fine with TTL. Am currently coding something for the SC28L92 so we'll see on that, but from what I read in the data sheet it should be fine as well.

Output slew-wise, I have that disabled in both my existing 6502GPD rev B design (uses ATF1504 7ns and (so far) in my new Blue816 v2 design (i.e. this 65816 one) which will use a ATF1508.
I might try enabling it to see if it helps with the above mentioned speed issues with my 6502GPD...

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

ATF1508AS-7JX84 so the 7.5ns version