24) PLA
PLA, "programmable" logic array, it is located North from the random logic area in the silicon.
And if you ask me, the layout of the PLA basically looks pretty much like a part of the 6530 ROM area.
It's big, and it's easy to mess things up while dissecting it, so I broke it into 9 parts:
East to West 24a)..24i).
The instruction Byte from the instruction register [see 21)] enters the PLA at the East in inverted and non_inverted form.
T0# and T1# from the first sequencer [see 22a)] enter the PLA from the South East.
T2#..T5# from the second sequencer [see 22b)] enter the PLA from the West.
They connect to horizontal PolySilicon traces which form the rows of the PLA, connecting to inputs of the NOR gates.
Most of the colums are just NOR gates, means the PLA outputs are supposed to be high_active.
NOR gates are vertical metal traces with a pullup resistor (FET) at the North ends,
and with FETs switching to GND attached to them.
FETs switching to GND are controlled by some of the horizontal PolySilicon traces.
The South end of the vertical metal traces is the PLA output.
But in order to save chip space, the designers had routed three signals through otherwise dead PLA NOR gates:
24:IRQP#, 89:RDYP, 90:RES.
Three more of the NOR gates (or "PLA product terms") are not used: 107:, 114:, 123:.
And we have some product terms which are a bit different from the others:
RDY1# goes into 80:T0.BR,
108:Tx.PSH_PUL goes into 92:T2.ANY_ABS and 99:T3.ANY_ABS,
136:Tx.PSH_PUL_ goes into 145:Tx.IMPL together with I0 from the instruction register.
The names for the product terms are from the original MOS schematics with the ROR bug,
that's ROR instructions missing, so don't wonder that the word "ROR" doesn't show up in them.
Now for the notation I have used for the product terms in my schematics:
'101:T4.IND_Y' means that product term 101 is active (high) during state T4, for addressing mode 'indirect Y'.
Tx means, that a product term is valid for all of the states.
//Note, that the PLA does not check for state T6, T6 is handled in the random logic area.
In the MOS 6502 schematics, the designers deliberately had counted the product terms from West to East,
starting with '1'.
Deliberately means, that they had included the three signals 24:IRQP#, 89:RDYP, 90:RES which
technically are just routed through the PLA as product terms, despite that they are no PLA product terms.
And they also had included the vertical GND metal traces of the PLA into the count, that's:
7:GND, 23:GND, 41:GND, 59:GND, 79:GND, 100:GND, 117:GND, 135:GND.
;---
I checked twice, and I think that my schematic for the PLA is correct,
but you better check if these 3000+ spots are with or without a FET again.
Speaking of it, now for the bonus material for those who might want to code something
like a little C program which highlights which PLA term is active in the instruction table.
If you take my PLA schematic, and rotate it clockwise by 90°, you notice from left to right:
one row of dots is red, 4 rows of dots are yellow, 4 rows of dots are yellow again, and so on.
A dot means, that a FET switching to GND is present in this location.
Now for a list of manually generated (so you better check) hexadecimal numbers.
One number per line in the text file, which stands for one PLA product term,
when converting the hexadecimal number to binary:
a binary '1' means FET present, a binary '0' means no FET there.
//Binary number is right adjusted, and the "special" product terms have a comment attached to the hexadecimal number.
Point is, that these hexadecimal numbers were my intermediate step between dissecting the silicon and drawing the schematic.
Attachment:
24_pla.txt [1.81 KiB]
Downloaded 57 times
Plus a text file from Frank with the names of the product terms.
Attachment:
MOS650x_decode_rom.vh.txt [4.53 KiB]
Downloaded 45 times
;---
Soptted 14 cases where two PLA product terms generate identical results:
Code:
51:T3.IND_Y = 2:T3.IND_Y
61:Tx.ROLx_ASLx = 121:Tx.ROLx_ASLx
62:T5.JSR = 116:T5.JSR
64:T0.TYA = 5:T0.TYA
68:T0.TXA = 11:T0.TXA
101:T4.IND_Y = 45:T4.IND_Y
102:T3.ABS_X_Y = 47:T3.ABS_X_Y
106:Tx.JMP = 34:Tx.JMP
119:T3.PULA_PULP = 29:T3.PULA_PULP
127:T1.ADC_SBC = 66:T1.ADC_SBC
128:T0.BIT = 75:T0.BIT
130:T4.RTI = 43:T4.RTI
136:Tx_PSH_PUL = 108:Tx_PSH_PUL
142:T4.ABS_X_Y = 77:T4.ABS_X_Y
;---
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