Hi all,
A question I've been asking myself is can multiple W65C816s all be connected to the same 'main' memory and run both concurrently and completely transparently to each other? It's a topic that's come up in this
Logisim thread where I've been cheerfully confusing Dr Jefyll with my vague explanations.
Another question I've been asking is "what level of completeness should I have before posting?". And for this I don't have a good answer. Too soon and this project could get stuck on paper being endlessly re-designed; too late and I either present what I've done fait accompli or I get blocked on something I just cannot do on my own.
In terms of just this timing circuit when I post is probably not that important so with no further ado, here's my plan:
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SRAM access times nowadays are fast compared to the '816. Even with random reads and writes it should be possible to be in and out of a 10ns SRAM within about 15ns. Compare that to a full '816 instruction cycle of (say) 75ns and that SRAM is sitting idle for the majority of the time.
A write cycle is simple to deal with. I can assume that write data on the DATA pins will be valid before at least SEL7 (from tMDS on the data sheet). The '816 doesn't care when I write it into RAM so I'm going to do that right (ha!) at the end during SEL8.
A read is a bit more complicated. If I understand correctly the read data needs to be valid on the DATA pins at least 10ns before PHI2 goes low but then has to be held for at least another 10ns after that. If I start doing the READ at SEL8 I'll probably get data back only 5ns before the PHI2 goes low. Probably that will work, looking at the performance others on this forum are getting. If it doesn't I can move the READ/WRITE window to SEL7 instead but that eats into my address decode time. Anything after the data has been read from SRAM is easy to deal with as I can latch it and then present it to the '816 for as long as necessary.
Taking a look at an (asymmetric) '816 clock cycle I can generate it from the SELECTOR signal below:
Attachment:
Selector Signal Small.jpg [ 92.03 KiB | Viewed 1153 times ]
PHI2 is just
SEL0 OR SEL2. Or at least it is in this picture. I've since shortened the low part of the cycle even further and I am using
SEL0 OR SEL1. (Can a W65C816S6TQG-14 handle the timings above? I pretty certain it can. Can it handle them at 3.3V? uh, I hope so)
You've probably seen where this is going now.
If the first '816's PHI2 clock is generated using
SEL0 OR SEL1 and its memory access window is in
SEL8 then
the second '816's PHI2 clock can be staggered and generated using
SEL2 OR or SEL3 and its memory access window will be
SEL0.
The third clock will be
SEL4 OR or SEL5 and its memory access window will be
SEL2 etc...
Five potential memory access windows allows for five '816s as below:
Attachment:
Memory Access Small.jpg [ 104.25 KiB | Viewed 1153 times ]
I think the principle seems sound. Each '816 can operate entirely independently of the others without ever having to wait for a chance to access memory. The actual timings I've presented here are best case and are generated using a 67MHz clock giving each '816 an effective 13.3Mhz operating frequency. The asymmetric duty cycle means the low cycle will be running at an effective 22.2Mhz which, again, will probably be fine for the W65C816S6TQG-14 at 3.3V. I think I'm more likely to run into issues in the 15ns memory access time.
Even if I have to drop to a 40Mhz clock to give me 25ns SELECTOR windows that still gives me five '816s each running at 8MHz; plenty of processing power. Practically I only have 40, 50 and 67MHz clock oscillators so... those are my choices. Testing-wise I'll run a 5MHz clock (the slowest 3.3V clock I have that's not in KHz) and I also still need to design some sort of single step circuit.
The circuit for generating the SELECTOR signals continues in the next post as the image is quite big.