Main thread: 6509 dissection

Another dissection brought to you by Frank Wolf and ttlworks.

While we did the first 6509 dissection, we had focused on what makes the 6509 different from the 6502.
That's why he had ignored the pins\pads: RES#, NMI#, IRQ#, RDY, SYNC,
since the logic attached to these pins is supposed to be more or less identical to what's in the 6502.

And that's why we do them now.

Note:
For consistence with Frank's notation, low_active signals are named foo#, not /foo.

Orientation for all the chip pictures: PHI1(in) is North.

Eagle 6.4 schematics for my schematic pictures in this thread,
just in case if somebody needs them.

Note: KiCad is supposed to be able to import these schematics,
unfortunately it doesn't seem to be possible to disable the layers 'name' and 'value' in KiCad schematics,
so making my schematics look nice and clean in KiCad will require some work, sorry.

A picture of the 6509 silicon, with the interesting areas marked.
The dark green areas in the picture went covered by the previous 6509 dissections.



Just as a reference, another picture of the 6509 silicon without the markings.

0) NMI#

//Falling edge at the NMI# input triggers a non_maskable interrupt.

There is a weak pullup resistor (FET) tied to the NMI# pad, 20 kOhms maybe.
Plus the usual ESD protection circuitry.

The Signal from the NMI# pad goes through two inverters,
which are feeding a transparent fully static latch.

The static latch samples the inverted/buffered NMI# signal at PHI2,
and gives out NMIP#.

NMI# and NMIP# have the same polarity.

1) IRQ#

//IRQ# input low triggers an interrupt. Interrupt can be masked/disabled with I Flag = 1.

Like with "0) NMI#", the IRQ# pad has a weak pullup and ESD protection.

The low_active IRQ# signal goes through two inverters, which are feeding a fully transparent static latch.

The static latch samples NMI# during PHI2.

The output of the static latch is sampled by a dynamic latch during PHI1,
which gives out the low_active IRQP# signal.

2) RES#

//RES# input low puts the CPU into a reset.

The game isn't too different from "1) IRQ#".

The RES# pad has ESD protection, but no pullup.

The low_active RES# signal goes through two inverters, which are feeding a fully transparent static latch.

The static latch samples RES# during PHI2.

The output of the static latch is sampled by a dynamic latch during PHI1,
which gives out the high_active RES signal.

3) SYNC

//When the CPU reads an instruction from the data bus, SYNC output goes high during PHI1 for the rest of that cycle.

Just a non_inverting driver, fed by the T11 signal from the sequencer, driving the SYNC pad.

4) RDY

//RDY input low halts the CPU during read cycles.

RDY pad has a weak pullup plus the usual ESD protection.

RDYP is the buffered RDY signal (which has the same polarity like RDY).
RDYP goes to the "ready logic" inside the CPU.

The RDY signal is sampled with a transparent latch at PHI2,
the output of said latch is sampled with another transparent latch at PHI1,
which then gives out the inverted RDY1# signal.
RDY1# low enables PLA product term 80 "T0.BR".

That's all for now.