tokafondo wrote:
I'm not sure that it would be easy to have address decoding covered from voltages from 1.8 to 5.5, and speeds from zero to 8, 14 or even more Mhz.
Any implementation will have to make compromises depending on the use case, for starters that voltage range is going to be pretty restrictive on what you can do. But you can probably assume 5V use on a breadboard?
BigDumbDinosaur wrote:
On paper, 20 MHz is readily attained with a discrete logic system, assuming the use of 74AC or 74AHC parts. My POC V1.2 unit achieves that with timing headroom to spare, but doesn't generate the A16-A23 bits.
V1.3 is essentially the V1.2 glue logic, with additional logic to expose RAM beyond bank $00. The 16 MHz maximum speed limit with V1.3 is due to the part of the logic that prevents mirroring of ROM and I/O outside of bank $00. The extra prop time through that section prevents clock-stretching from being effective at 20 MHz, causing ROM and I/O access failures.
V2.0, which is in work, implements glue logic with a single CPLD. It'll be interesting to see how fast it will run.[/color]
Interesting, I need to look at your circuits in more details
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