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PostPosted: Tue Nov 23, 2021 9:10 am 
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plasmo wrote:
What you are describing looks kinda like this (attached photo).

2"x4" pc board with single row of 40 pins that plug into solderless breadboard. In the 40-pin connector are 16 address lines, 8 data lines, clock, reset, 6 control lines, 6 spares and +5V/gnd. A 64-macrocell CPLD provides flexibility for experimentation. It was originally designed for 6502, but only small modifications are needed for 65816. 65816's high order addresses can connect to the 6 spares.
Bill


Thanks.


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PostPosted: Tue Nov 23, 2021 10:45 am 
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I'm realizing that one of the differences of such an adapter from a SBC is that you can use the voltage you would need, instead of fixing it at certain level. The user should then use capacitors outside the adapter.

...unless there is some kind of right for any voltage capacitor value that would allow to integrate it in the adapter.


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PostPosted: Tue Nov 23, 2021 12:16 pm 
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Capacitors just have a maximum rated voltage. Provided your working voltage is within that, you're fine. (Granted there are some complications like DC Bias, frequency response, etc, but generally speaking you can ignore such considerations on a hobbyist SBC's decoupling caps)

Ideally you want your decoupling capacitors as close to the power pins of the devices they are decoupling - the further away they are, the greater the impedance, the less effectual they'll be. I would therefore strongly recommend putting the capacitors on the adapter.

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PostPosted: Tue Nov 23, 2021 12:24 pm 
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Experimenting with supply voltage and clock speed might well be something to do with such a breadboardable module - so, as well as keeping the clock external, keeping the power regulation external is a good plan.

But indeed, decoupling capacitors are not specific to the voltage of the supply, and should be close to each chip, so they should be on-board.


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PostPosted: Wed Nov 24, 2021 9:12 pm 
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Well... With my limited skills and ignorant of all design rules, I tried to design this by using Kicad. This is not finished

Attachment:
File comment: KiCad schematics
Portapapeles01.png
Portapapeles01.png [ 61.78 KiB | Viewed 753 times ]


For me, it's a mess to try to have just the '816 and the companion chips that will decode the address bus in a compact card like, having the chips in both sides of the board, with all the buses going from here to there like it's needed.

Attachment:
File comment: PCB design
Portapapeles02.png
Portapapeles02.png [ 122.61 KiB | Viewed 753 times ]


There are two options: make the PCB bigger, or change the format and try a sandwich of small boards that will have both a PDIP 40 female socket and a PDIP 48 male header.

Attachment:
File comment: 3D view - unfinished
Portapapeles03.png
Portapapeles03.png [ 463.27 KiB | Viewed 753 times ]


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PostPosted: Wed Nov 24, 2021 9:33 pm 
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It's often the case that relaxing the PCB size makes things a lot easier. Once you have a layout which works, it might then be possible to see ways of making it smaller. If you don't have some strict size constraint, consider relaxing it.


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PostPosted: Wed Nov 24, 2021 11:10 pm 
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Regarding trace routing, you might find a '573 latch easier to deal with than a '373. The function is identical. But the '573 pinout is sensible and predictable. (By comparison, the '373 is scrambled and illogical -- just goofy, IMO! :P )

Quote:
a PDIP 40 female socket
For the '816, you mean? You could save a lot of space by using the PLCC version instead. (Or even the flat pack version, although in that case you'd be unable to use a socket.)

Quote:
This is not finished
Yes, there are some errors in how LE and OE are driven on the '373 and in how OE is driven on the '245. :wink:

-- Jeff

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PostPosted: Sat Nov 27, 2021 3:04 pm 
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UPDATE: Revised the schematics and deleted the wires. All is referenced by labels now. I believe that I copied the 816SXB schematic part related to decoding the extra address bus.

Attachment:
File comment: Updated schematics
Portapapeles01.png
Portapapeles01.png [ 217.97 KiB | Viewed 682 times ]


Edit: found a mistake in the schematics.


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PostPosted: Sat Nov 27, 2021 5:02 pm 
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tokafondo wrote:
UPDATE: Revised the schematics and deleted the wires. All is referenced by labels now. I believe that I copied the 816SXB schematic part related to decoding the extra address bus.

Attachment:
Portapapeles01.png


Edit: found a mistake in the schematics.


You are driving LE on the '573 and DIR on the '245 with the wrong thing. You're driving both of these with the inverse of BE. OE on the '573 should be driven with the inverse of BE. LE should be driven with the inverse of PHI0 (latch transparent when clock low, latched when clock high). DIR on the '245 should be driven with RWB (signals driven from A to B when RWB=1, B to A when RWB=0).
Also, OE on the '245 should be !(BE & PHI0) - i.e. output enabled when BE and PHI0 are both high.
Also, why are you using a 74LV03? This is a device with open drain outputs, so would need pull up resistors on the outputs in order to work correctly. Even with those resistors present it would still be slow. You should use gates with totem pole outputs here.


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PostPosted: Sat Nov 27, 2021 5:34 pm 
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Thanks for comments and corrections.

kernelthread wrote:
You are driving LE on the '573 and DIR on the '245 with the wrong thing. You're driving both of these with the inverse of BE. OE on the '573 should be driven with the inverse of BE. LE should be driven with the inverse of PHI0 (latch transparent when clock low, latched when clock high). DIR on the '245 should be driven with RWB (signals driven from A to B when RWB=1, B to A when RWB=0).
Also, OE on the '245 should be !(BE & PHI0) - i.e. output enabled when BE and PHI0 are both high.
Also, why are you using a 74LV03? This is a device with open drain outputs, so would need pull up resistors on the outputs in order to work correctly. Even with those resistors present it would still be slow. You should use gates with totem pole outputs here.


Thanks. It seems I haven't studied the SXB schematics as good as needed, so I have to take a closer look.

I'm using the LV03 to leave the 1.8V door open, and I found the LV03 to be the only chip that can use such a low voltage.


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PostPosted: Sun Nov 28, 2021 1:16 pm 
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tokafondo wrote:
Thanks. It seems I haven't studied the SXB schematics as good as needed, so I have to take a closer look.

I'm using the LV03 to leave the 1.8V door open, and I found the LV03 to be the only chip that can use such a low voltage.


Shameless plug, but if you need help figuring out the 65C816 bus, I go into a lot of details on how to demultiplex it in my YouTube series, for a few episodes starting with https://www.youtube.com/watch?v=eVvno_Y ... qT&index=2

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PostPosted: Sun Nov 28, 2021 2:42 pm 
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akohlbecker wrote:
Shameless plug, but if you need help figuring out the 65C816 bus, I go into a lot of details on how to demultiplex it in my YouTube series, for a few episodes starting with https://www.youtube.com/watch?v=eVvno_Y ... qT&index=2


Thanks. Are there alternate, better ways to decode the address bus? I think I've read that this decoding works up to a limit, imposed by the propagation delays, so it doesn't work when clocking the 65816 too high.

I have a '265 at home, and it would be nice to have a way to test if the full address bus featured in that chip is better than the 816's decoded one, speed wise.

But as the internal ROM monitor that the '265 has only works, certified up to 8 Mhz, external software would be required for that tests.


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PostPosted: Sun Nov 28, 2021 2:55 pm 
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tokafondo wrote:
akohlbecker wrote:
Shameless plug, but if you need help figuring out the 65C816 bus, I go into a lot of details on how to demultiplex it in my YouTube series, for a few episodes starting with https://www.youtube.com/watch?v=eVvno_Y ... qT&index=2


Thanks. Are there alternate, better ways to decode the address bus? I think I've read that this decoding works up to a limit, imposed by the propagation delays, so it doesn't work when clocking the 65816 too high.

I have a '265 at home, and it would be nice to have a way to test if the full address bus featured in that chip is better than the 816's decoded one, speed wise.

But as the internal ROM monitor that the '265 has only works, certified up to 8 Mhz, external software would be required for that tests.


For sure, to run at high speeds, you're going to need a PLD, I don't think it is doable with discrete logic. That also depends on which peripherals you want to talk to with your CPU.
Right now I'm planning to run at 4Mhz and I think discrete logic will be fine for this, and I'll move on to an ATF22V10-7 to get more speed, or even an ATF1504 to implement the whole thing.

Still, building it first at a slow speed will help you understand the intricacies better and figure out the best way forward for your particular use case

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PostPosted: Sun Nov 28, 2021 3:38 pm 
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akohlbecker wrote:
Still, building it first at a slow speed will help you understand the intricacies better and figure out the best way forward for your particular use case


Thanks. In this case, this is about creating an adapter that would already decode the bus for the user, just for use in breadboards. So it seems to me that having the CPU running at high speeds won't be that easy, as high speeds in breadboards are not that easy to reach. Or are they?


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PostPosted: Sun Nov 28, 2021 6:09 pm 
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tokafondo wrote:
Thanks. Are there alternate, better ways to decode the address bus? I think I've read that this decoding works up to a limit, imposed by the propagation delays, so it doesn't work when clocking the 65816 too high.

My POC V1.3 unit, which has 112KB of RAM available, is entirely discrete logic and runs at 16 MHz. It can go somewhat faster, but 16 MHz is guaranteed to be stable with worst-case logic timings.

akohlbecker wrote:
For sure, to run at high speeds, you're going to need a PLD, I don't think it is doable with discrete logic.

On paper, 20 MHz is readily attained with a discrete logic system, assuming the use of 74AC or 74AHC parts. My POC V1.2 unit achieves that with timing headroom to spare, but doesn't generate the A16-A23 bits.

V1.3 is essentially the V1.2 glue logic, with additional logic to expose RAM beyond bank $00. The 16 MHz maximum speed limit with V1.3 is due to the part of the logic that prevents mirroring of ROM and I/O outside of bank $00. The extra prop time through that section prevents clock-stretching from being effective at 20 MHz, causing ROM and I/O access failures.

V2.0, which is in work, implements glue logic with a single CPLD. It'll be interesting to see how fast it will run.

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