I’m working on a ttl implementation of the 6502 and I’m at the end and coding up the control lines. I noticed the INC/DEC instructions for the abx addressing mode takes the same number of cycles regardless of whether or not there’s a page cross. Other instructions might have timing constraints and can’t afford to skip the cycle, but INC & DEC just don’t seem to need it? I’ve even coded them to work with one less cycle (unless there’s a page cross).

Is there a reason why they do this?
Thanks,
Jason

Indeed, I just checked, and there's always an extra read whether or not there's a page crossing.

I don't see any obvious reason, so I suppose it just fell out of the way the control logic is written - perhaps there was a chance to optimise which they missed, or perhaps the simplicity of doing it the same way saved a few transistors.

Edit: one way to look at this is that the 6502 is both a design and an implementation. Because it aimed to be low cost (and finished quickly) the implementation may include some compromises. (Indeed, a design may also include some compromises, to aid the implementation, or to aid verification, or testing, or documentation.)

Thanks for the update. I'm certainly not suggesting they could have done better, but making sure I wan't missing something. As far as I'm concerned the 6502 is fantastic piece of engineering. Having gone through the process of building one (with the advantage of their schematics) I have nothing but admiration for the team.

I forget which instruction it was but there was one that had all the buses in action at the same time, which isn't that unusual, but in this instance the buses were each working on a different task. So I think we should stop talking about it's 'pipelining' capabilities and instead boast about it's 'parallelism'

This pattern shows up in a number of places and it's timing related.

The processor needs an additional cycle to perform the addition by 1 with the ALU. In the meantime, it has to keep the external bus busy with a minimum of side effects. There is no such thing as an "idle" bus, so it will just plow along either reading or writing data with whatever bits happen to be active on the data and address buses. Leaving AB and DB with R would re-read the same value and overwrite the increment result, but flipping to W effectively makes it a no-op. That's how you end up with the extra write.

Btw, it gets worse with ABS,X. Here the CPU has to do an additional 'no-op' read to buy time for the carry addition with the address:

INC $2080,x (with x=0x90)

1: external: read instruction
2: external: read 0x80
3: external: read 0x20, internal: performs address addition on low byte: 0x80 + x (0x90) -> 0x10, c=1
4: external: read from $2010, internal: performs address addition on high byte (w/carry): 0x20 + c (1) -> 0x21
5: external: read from $2110 (now has correct address)
6: external: write unchanged value to $2110, internal: performs actual increment
7: external: write actual result to $2110

What's neat is that this technique helps save a cycle on read operations like "LDA" with ABS,X when the read happens on the same page, since step 4 amounts to a speculative read. When C happens to be 0 the address was already correct and the instruction is done. If C is 1 (across page boundary), it has to do an additional read with the correct address.

I think all of us here on this forum agree that the 6502 is fantastic piece of engineering!

But they could, in fact, have done better. As Ed noted, they were under pressure, and had to include some compromises.

To be clear, on NMOS 6502 the issue affects the Abs,X version of all Read-Modify-Write instructions featuring that mode. These are INC, DEC and the four shift instructions, ROL, ROR, ASL and LSR. The extra cycle always appears, even when no page crossing occurs -- and in that case it's a wasted cycle. (When there's no page crossing there's also no carry that needs to be added into the high byte of the address.)

This is one of several issues that received attention when the 65C02 (CMOS '02) was released. But, interestingly, only ROL, ROR, ASL and LSR got updated, whereas INC and DEC still wastefully include the extra cycle even when no page crossing occurs.

Also interesting (for 'C02 fans, at least) is the fact that 'C02 data sheets from Rockwell and WDC both fail to correctly document the update. For more on the Abs,X R-M-W mystery see this post.

-- Jeff

ps- welcome, Dre9K !

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Thank you!