kernelthread wrote:
One little gotcha with these FT24x chips is that, while the RD strobe is active low, the WR strobe is active high. I almost got burnt by that one but caught it in a final check just before I sent the PCB for fabrication.
I was slower than you; I discovered FT245_WR is active high AFTER I've sent off the pc board, so that's is one of the two problems the added 74LS10 fixed. However, that's not the problem why I can't write to FT245. It is something else...
Michael wrote:
ok, wait a minute. after the 6502 performs the write clock cycle to $8000+x it will go back to read at PC in the FT245 region during the next clock cycle and that's when it will read that fifth character from the FT245. So that fifth character could actually be the opcode portion of the next instruction you'd like to send to the 6502. very cool!
Michael,
STA abs,X takes 5 cycles. The first three cycles fetch the op code from FT245, the next two cycles access the RAM so does not involve the instruction stream from FT245. So the data I sent to FT245 to execute the STA $8000,X instruction are 0x9D, 0x0, 0x80. However, as you've pointed out that the two memory cycles to RAM can not execute because FT245 receive FIFO is empty (/RXF negated), so the execution of the RAM access is suspended until next data is received in FT245's FIFO. It is somewhat confusing that the execution of current opcode is pending on receival of next opcode. It is akin to instruction pipeline such that if the pipeline stalled fetching next instruction, the current instruction won't finish execution.
In my setup Windows' TeraTerm is connected to FT245. This is the program I sent to TeraTerm to load a small NOP,NOP,BRA to NOP" in RAM and then jump to RAM to execute it.
The first five instructions (C000-C004) set the reset vector to 0xEAEA and execute one or two NOP instructions, the next instruction (C005) is an illegal instruction for synchronization purpose. This is because the reset is somewhat unpredictable and can fetch extra opcode. The illegal instruction realigns the instruction fetch so next opcode will always be treated as an instruction. From C006 to C024 are instructions to copy a simple program into RAM. You'll notice "STA $8000,x" is 9D 00 80 like a normal STA $8000,X, but "INX" is E8 03 where "03" (or any data) is needed because INX takes two fetches to FT245 to complete. The last instruction is "JMP $8000", but you may notice I have two JMP. The second JMP (actually any data) is needed to start program execution by putting a byte in FT245 FIFO so /RXF is asserted.
Bill
Edit,
Frankly it is a pain having to pad instruction stream with extra data and understanding cycle-by-cycle behavior of each instruction, so my approach is to put together a bootloader in memory, jump to it so I can load normal 6502 program.
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