https://github.com/jmstein7/65c02_core

Hey, all! I'm trying my hand at a new FPGA implementation of the 65C02 ISA as an exercise in processor design, and I figured I'd share my progress here. Thus far, I've implemented all the structures and connections set forth on figure 2-1, page seven, of the WDC Data Sheet (Internal Architecture Block Diagram). And I've run all the control signals to the Instruction Decoder.

However, the ALU function, and the ISA, has not been implemented yet (because I haven't yet decided the best way to go about it. Maybe microcode?) Like I said, this is the first time I've tried my hand at processor core design.

Anyhow, feel free to have a look and, if you like, to tinker with what's there so far! Any input is welcome.

The top level of the design is "processor wrapper". Right now it's for the Artix-7, with a stand-in CMOD A7 target, but that is subject to change.

Best,

Jon

Github: https://github.com/jmstein7/65c02_core

PS I've been working on this for a week, so it wouldn't hurt to have some fresh eyes on it, to boot.

Good luck on your new FPGA project! If you decide to go the microsequencer route you could look over my code for some ideas: https://github.com/MicroCoreLabs/Projects/tree/master/MCL65

Ted,

Thanks for the encouragement! Now that all the moving parts seem to be in place, I just need to figure out how to choreograph that movement I have to say, having tried this, I've so much respect for guys like you and others here who actually have completed entire cores.

Jon

I had some time to work on this, so I pushed the new material, and changes, to the repository:
https://github.com/jmstein7/65c02_core/tree/main

Jon

PS Time to do the ALU!

good choice! the 65C02 is a pretty simple Processor, perfect for educational projects like these.
I once made a 65C02 in a logic simulator called "Logisim Evo HC".

though there is a very important detail that can make the whole project a lot easier (or harder depending on knowledge):
do you aim for a prefect replica of the original hardware, down to the data paths and decoding logic? or do you just want something that is software compatible and is otherwise your own design?

with my project i didn't want to replicate the exact inner workings of the CPU as i felt i would learn more by doing those things by myself from scratch. besides the Instruction set and pins on the virtual processor being identical to the real 65C02, almost everything on the inside is very different.
I still use it to this day to test programs i would run on my real life SBC, as a logic simulator is a lot more in-depth and customizable than a regular emulator.

you can take a look at my spaghetti if you want, maybe it gives you a few ideas for your own Processor.
though be warned that i did not intent for anyone besides myself to look at it, so it might be hard to understand what is going on...

either way, good luck with your project!

One thing I would love to have is a simple way to figure the overflow flag on SBC.

Jon

Did you already figure it out for ADC? Correct me if I'm wrong, but there should be absolutely no difference between ADC ~operand and SBC operand, including the result and all flag effects.

[I suppose the one caveat is that you need the nines complement instead of the ones complement if D is set, but in BCD mode V is a bit of a crapshoot anyway ...]

_________________
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Mike B. (about me) (learning how to github)

that is one i also struggled with, you can find it in my core, hidden deep inside the "ADDER" subcircuit.
because you can switch between Binary and BCD mode my simulated core has 2 seperate Adder and Overflow circuits.

with the bianry one i split the 8-bit Adder into 2 parts, a 7-bit Adder for the lower bits 0-6, and a 1-bit Adder for the upper 7th bit.
the Carry output of the 7-bit Adder went directly to the Carry input of the 1-bit Adder, forming a complete 8-bit Adder while giving me access to the 6th bit Carry.
you then take the Carry from both Adders and XOR them together, the output the Overflow flag.

so basically, whenever the 6th bit overflows into the 7th bit, or the 7th overflows without the 6th overflowing as well, the Overflow bit gets set.


for BCD the whole circuit is a lot more complex.
just talking about the Overflow flag though, i basically did:
take bit 7 of Input A and XOR it with bit 7 of Input B
take bit 7 of Input A and XOR it with bit 7 of the Output
then take the output of both XOR's and NAND them together.
the output of the NAND is the Overflow flag when BCD is enabled.

honestly i couldn't tell you what is happening in that circuit, but it seems to work. BCD is weird.


isn't the 65C02 using two's Complement in Bianry mode?

Here is my rather sloppy solution for ADC:


It has to be different for SBC , because you're effectively adding a negative number, right?

the circuit i've posted works for both ADC and SBC.
both Addition and Subtraction use the same exact circuit, only difference is that when subtracting you invert all the bits of Input B (and in BCD Mode you do 9's Complement).
that's the reason you have to clear the Carry flag when doing Addition, but set it when doing Subtraction.

so barry was right, it is applying 1's Complement in Binary mode, if the 6502 used 2's Complement you would need to clear the Carry flag for Subtraction as well.

So, for SBC, I just need to XOR the resulting Carry Bit with the "carry bit" of bit 6 (of the result)?

I just pushed another update to GitHub - I finished writing the ALU over the weekend; now I'm going to test the heck out of it. Thanks for all the help with the V flag - I think I nailed it.

Jonathan

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks, Garth, that's great (and helpful) stuff!!!!!!!

I had some time to work on this today, so I pushed another update.

https://github.com/jmstein7/65c02_core

It's time to program the op codes in!