Joined: Fri Aug 30, 2002 1:09 am
Posts: 8544
Location: Southern California
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The pipeline is quite short (only fetching the next instruction's op code while finishing an already-executing instruction), and you don't have to worry about stalls resulting from things like refilling the pipeline after a branch. (I'm not familiar with MIPS, so I don't know if that's what you're referring to.) The only thing I can think of to comment is that if the IRQ\ goes down during phase2 of the operand fetch of a branch instruction, it will, according to my tests on the '816, take the branch if appropriate and sometimes execute one more instruction before the interrupt sequence starts. With a quick look at my test results from quite a few examples I tried, I don't seem to be able to nail down the pattern. Also, see this topic regarding whether an interrupt can delay the execution of the instruction immediately following an SEI instruction. But generally, like Lee says, you don't have to worry about it.
Edit: See also the lengthy topic A taken branch delays interrupt handling by one instruction (about the NMOS '02). It has more links too. I should probably go back and re-read it myself.
Edit2: See also the topic If an interrupt occurs on a BRK instruction, regarding the NMOS 6502 bug. The NMOS had other bugs too, all corrected in the CMOS version and the 65816. I have put all the NMOS-CMOS differences together in one article at http://wilsonminesco.com/NMOS-CMOSdif/ . (Let us know if I'm getting too far off of what you were thinking of.)
_________________ http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
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