byte length of 65816 instructions

[jeffythedragonslayer]

Is the byte length of 65816 instructions a function of only the addressing mode used and not which register is being accessed or the opcode, just like the 6502?

[kernelthread]

Not quite sure what you mean by "not a function of the opcode". Clearly the length of the instruction depends on the opcode since the opcode determines which instruction it is.

As well as the opcode, the byte length depends on the state of the m and x flags. For example

LDA #0 is 2 bytes (A9 00) if m=1, but 3 bytes (A9 00 00) if m=0.
LDX #0 is 2 bytes (A2 00) if x=1, but 3 bytes (A2 00 00) if x=0.

Note also that if, for instance, m=0 but x=1, then LDA #0 is 3 bytes, but LDX #0 is 2 bytes. So it does depend on the register where there are similar instructions for different registers.

[Dr Jefyll]

kernelthread wrote:

the length of the instruction depends on the opcode since the opcode determines which instruction it is.

Right. Dragonslayer, all 65xx instructions begin with a one-byte opcode, and in some cases that's all that's necessary. For example, ROL is an instruction that can take several forms, and the form of ROL that rotates the accumulator requires nothing more than the opcode. There's nothing further to add, because the opcode is sufficient to tell the whole story.

But ROL also has a form that rotates a memory location in Zero Page, in which case there's a different one-byte opcode and it gets followed with a byte that supplies the Zero Page address. Similarly, ROL can address an absolute memory address, in which case the relevant opcode gets followed by two bytes of address information. (And for some instructions the '816 has long modes that use three bytes of address information.) So, the address mode has an effect on the total instruction length.

In other cases, the byte(s) following the opcode contain an immediate operand that'll directly interact with one of the processor registers. And, as kernelthread has explained, the length of the registers may be either 8 or 16 bits (according to the m and x flags). Thus, the length of instructions which include an immediate operand will be 2 or 3 bytes (including the opcode).

-- Jeff

[jeffythedragonslayer]

kernelthread wrote:

Not quite sure what you mean by "not a function of the opcode". Clearly the length of the instruction depends on the opcode since the opcode determines which instruction it is.

I tried putting together a table with all the 6502 opcodes as the rows and all the addressing modes as the columns and filling in the cells with the byte lengths. Someone more experienced than me at 6502 was confused why I was trying to do this and pointed out every column would have the same number all the way down (although some cells are n/a). That's what I mean; you can figure out the byte length from the addressing mode and don't need to know the opcode.

Thanks you both; so to summarize if I understand correctly, the byte length of a 65816 instruction is a function of its addressing mode as well as the m and x flags.

[Dr Jefyll]

jeffythedragonslayer wrote:

so to summarize if I understand correctly, the byte length of a 65816 instruction is a function of its addressing mode as well as the m and x flags.

Yup. And, to be clear, the list of address modes (along with zero page, absolute and all the rest) also includes implied mode (such as ROL accumulator, which I mentioned) and immediate mode (which, as I said, causes the operand after the opcode to directly interact with one of the processor registers). Immediate mode is the only one for which the m and x flags have a bearing on instruction length.

[BigDumbDinosaur]

jeffythedragonslayer wrote:

Thanks you both; so to summarize if I understand correctly, the byte length of a 65816 instruction is a function of its addressing mode as well as the m and x flags.

“Byte length” is not a good choice of words when describing machine instructions. A byte only has one length—eight bits. The proper term is “instruction size,” which refers to the number of bytes that make up an instruction. That number can range from one to four, depending on the MPU being programmed. As the opcode is always a single byte—and the first one in a multi-byte instruction, the operand size is what will vary.

There are some instructions that can operate on either the accumulator or memory. The presence or absence of an operand determines that, and determines which opcode will be assembled for the instruction in question. If there is no operand, as in Jeff's ROL example,¹ the accumulator is the implied address. If there is an operand, ROL will left-rotate the content of the memory cell pointed to by the effective address. ROL can be used on either zero (direct) page or absolute memory, which means the possible instruction size for ROL can be one, two or three bytes.

As Jeff notes, the m and x bits in the 65C816's status register (SR) affect instruction size only with immediate mode addressing. For example, if m = 1 and I write LDA #$1234, only the $34 part of the operand will be loaded into the accumulator, and the $12 part will be interpreted as the opcode for the next instruction. The instruction size will be two (opcode and one-byte operand).

On the other hand, if m = 0 and I write LDA #$1234, $1234 will be loaded into the accumulator. The instruction size will be three (opcode and two-byte operand).

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¹Some assemblers use the operand A to signify accumulator address, which is actually part of the original MOS Technology assembly language standard. In such a case, the instruction would be written as ROL A.

[BigEd]

jeffythedragonslayer, it might be that when you say 'opcode' you mean something closer to 'mnemonic' - you mean the three-letter abbreviation for the operation.

Whereas it's more usual to mean the instruction byte, which is indeed a combination of the mnemonic and the addressing mode (and the machine mode).

[jeffythedragonslayer]

BigEd wrote:

jeffythedragonslayer, it might be that when you say 'opcode' you mean something closer to 'mnemonic' - you mean the three-letter abbreviation for the operation.

Whereas it's more usual to mean the instruction byte, which is indeed a combination of the mnemonic and the addressing mode (and the machine mode).

Thanks, it sounds like a lot of people get mmenmic/opcode/instruction confused. I suggested nailing down this terminology to Ville and he did a big rename in WLA.