In a recent thread regarding a minimal ROM programmer, my mind began to wander to past 6502 projects I have done, some of them a little far fetched from the "norm". I didn't want to wander off topic on the other thread, so here is a very strange ROMless system I once made work.

Just wondering if anyone else tried this very bizarre scheme...

I had a 6502 running from a single 16K SRAM and no other ROM / RAM on the bus.
The 16K sram was mapped to the first 14 address lines.
On start, the SRAM is boot loaded with the code to run.
My IO was on address line 14.

Seems normal enough except when you consider the boot vectors!

What I did was connect address line 15 to the CE on the SRAM so it was disabled when the 6502 address the last segment of memory.
I also used weak pulldowns on the data bus so that data would read 0 when looking for the boot vectors.
This pointed the start of code to address zero, where I then had a jump out of zero page to my actual code.

Since the SRAM is loaded on boot, this worked perfectly and required no other components for an address decode scheme.
Probably seems pointless, but in my system it kept speed high and parts count low.

Brad

I like it!

However, I'm curious about the speed being kept high. I'm sure the pulldowns worked, but would they pull the bus low as rapidly as the RAM or IO would do? It seems to me the slowness of the pulldowns might limit your maximum clock rate. If I were in your situation (and assuming it's a WDC CPU being used) I think I'd replace the pulldowns with diodes, whose cathodes I'd attach to the VPB pin.

On the topic of unexpected approaches for ROMless systems, I hope you've seen my thread, Ultra-minimal 3-wire Interface boots up 65xx CPU's! (It's not a replacement for what you've done -- just something conceived in a perhaps similar spirit!)

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

That was a good read! Very out of the box thinking indeed.
Did you ever verify it in a prototype?

I am shacked up in a lodge at Kitchenuhmaykoosib Inninuwug right now for a school I.T. job I am on, so this forum is keeping me sane!
And yep, I did spell that from memory.

Brad

There is a similar approach in Z80 world where reset vector is at 0x0 and NOP is 0x0, but because of CP/M, RAM needs to start from 0x0 and ROM located in high memory. So the approach (an old design I don't recall the product name) is disable RAM at power-on reset and pull data bus to 0x0 with weak pull down resistors. The program will run NOP until first instruction in ROM; RAM is then enabled via ROM software.


Dr J's 3-wire bootstrap is very innovative. I was hoping he'll have similar idea for the simple EPROM programmer.
Bill

May I ask how SRAM was loaded, please?

So IO is active when A14 is low ($0000..$3FFF and $8000..$BFFF) and SRAM is active when A15 is low ($0000..$7FFF)?

With many of my 6502 projects, I push code to the SRAM via microcontroller. After loaded, the uc simply tristates and sleeps like a ghost.
In some designs (like this one), the uc does other work after boot. In this case, it became IO to an SDcard file system.

Taking it a step further (less chip count), I sometimes use ONLY the microcontroller - a tight assembly loop emulates ROM directly.
I am doing this right now on a Commodore PET project, putting PC loadable code into the option ROM socket.

In all cases, the "ROM" can be instantly (and in-circuit) loaded from a PC.

Brad

Still confused... Sorry.

How are you using A15 to select RAM and A14 to select I/O without additional address decode logic without overlapping/conflicting memory region?