28) Register $0A

Located between A14 pad and MA8 pad, East of Register $01.

Address control Register $0A:
Bit 0..5: not present, reads -1.
Bit 6: 1=block AM0..18 address counter increment. //REU DRAM memory address
Bit 7: 1=block A0..15 address counter increment. //C64\C128 memory address

Circuitry for the Register Bits is pretty much standard.

A RESET clears Bit 6 and Bit 7.

Bit 6 and Bit 7 are sampled with PHI1 in transparent latches,
go into some odd circuitry that generates outputs identical to the inputs (I had checked that a few times),
then the signals go into "31) tapeworm from hell":
R$0A.Q60 (high active) reflects Bit 6,
R$0A.Q70 (high active) reflects Bit 7.

29) Register $09

Located between A14 pad and MA8 pad, East of Register $0A.

Interrupt Mask Register $09
Bit 0..4: not present, reads -1.
Bit 5: enables IRQ after a VERIFY error.
Bit 6: enables IRQ generated after the end of a DMA sequence.
Bit 7: global IRQ enable (if cleared, IRQ pin is disabled).

Circuitry for the Register Bits is pretty much standard.

A RESET clears Bit 5, Bit 6, Bit 7.

Bit 5, Bit 6 and Bit 7 are sampled with PHI1 in transparent latches,
feeding two NAND gates which generate the IRQ enable signals:
IE5# (low active) = Bit 5 NAND Bit 7,
IE6# (low active) = Bit 6 NAND Bit 7.

IE5# and IE6# go to the IRQ circuitry attached to the Status Register $00,
which is located East from the Interrupt Mask Register Register $09.

30) Register $00

Located between A14 pad and MA8 pad, between Register $09 and the AM16..18 counter Bits.

Status Register $00
Bit 0..3: read 0. //chip version number, write has no effect.
Bit 4: read: BS input pin (bank select configuration), see "9) BS". //write has no effect.
Bit 5: read: VERIFY error flag. //write has no effect.
Bit 6: read: DMA sequence completed flag. //write has no effect.
Bit 7: read: inverted IRQ# pin. 1=IRQ active. //write has no effect.

Bit 5 and Bit 6 are cleared at RESET, also in the next PHI2_in cycle after reading the Register.
Note, that clearing the Bits overrides setting the Bits.

R$00.S5# (low active)(sampled with PHI1) sets Bit 5, see "23b) compare logic".
R$00.S6 (high active) sets Bit 7, see "31) tapeworm from hell".

IRQ# = NOT Bit 7. //IRQ# is "open collector output" with pullup resistor.
Bit 7 = (Bit 5 AND (NOT IE5#)) OR (Bit 6 AND (NOT IE6#))

The IE5# and IE6# (low active) IRQ enable signals are generated by NAND gates attached to
the Interrupt Mask Register $09, which is located West from the Status Register $00.

31) tapeworm from hell, also known as "the control circuitry".

It controls everything in the chip related to DMA.

Logic blocks that are spread out like a frog that did fall into a kitchen blender by accident,
wired together with interconnections that don't fit on a screen of any size,
that was my first impression.

Tried my best, but I have to admit that I'm not understanding the circuitry as a whole.
So I can't tell if I made errors while drawing the schematics, but there probably are some.

For those who enjoy reconstructing a cow from a truckload of burgers,
I had annotated the logic gates and transparent latches (128 in total)
in the polygonized picture and in the first schematics...

//Victor Andrade certainly is better at logic design than me and Frank.

For navigating the circuitry, my reference points were the D0io..D7io data bus
input/output lines of the registers North from that tapeworm from hell.

So much for "everything you never wanted to know about the 8726".
Edit: Frank is working on a transistor_level FPGA implementation of the 8726, but this will take some time.

6525 is next, because it would put us into a good position for aiming at 6522 and 6526.

I would like to mention, that decapping a chip and making microscopic pictures causes Frank laboratory costs of ca. 2k€,
and that small donations\tips to Frank might affect which chip gets what priority for a dissection...

Another magnificent piece of work - thanks for sharing!

I (we) underestimated the complexity of this chip considerably... but we're glad we got
through it. Now let's dig into the HDL conversion! (To be honest: I already started!

And thanks to 'ttlworks' for supporting these chips adventures! Without his help
this documentation would certainly not exists!

Just for the sake of completeness a comparison of the original microscope picture and the vectorized chip image:

MOS8726R1_vec vs. MOS8726R1_metal

Use the slider in the middle of the picture to see it!

Excellent work!

_________________
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

There's no word to describe how amazed I'm at this kind of work.

Feels like magic. I know it's not... but feels like it.

Congrats, and thanks for such an awesome work.