Hi,

Does anyone know when the 6502 was patented ? And has it expired ?

Thanks,
Rob

I don't know the exact answers you're looking for, but since it has been a couple of days an no one else has responded, I'll jump in anyway.

There's an interview with the inventor, Bill Mensch, that you can watch online. Go to http://silicongenesis.stanford.edu/comp ... sting.html , and go down a little past the middle and click on William Mensch. I've watched it two or three times in the past and took notes, but I guess they raised the software requirements so it doesn't work on my old computer anymore even though it did before. Back then I only had a 28.8kbps modem which made the streaming video extra lousy, but there was still some value in that poor-quality video. The sound was fine for an interview.

A few interesting things from the interview: The 6800 got the "8" from the PDP-8 which it partly copied, and the 6501 got the "1" from the PDP-11 which it partly copied. He had been at Motorola, and a bunch of them broke away on 8/19/74 and designed the first of the 65 family processors at MOS Technology. Mot sued them. The suit was baseless but it slowed them down. On Sept 8, 1975, an ad came out inviting people to see the 6502 at Wescon '75, at Moscone Convention Center in San Francisco IIRC. The first 1.5 years' worth of 6502's were all tested by hand on a hand-made board without parametric testing. In 1976, he had 6502's running at 10MHz which was unheard of at that time. If a part would pass the test at 2MHz, they'd mark it for 1MHz for sale. If it'd pass at 4MHz, they'd mark it for 2MHz, and so on. The 65c02 came out in 1980. At the time of the interview (1995), Bill Mensch said he thought the 65816 was probably the greatest-selling 16-bitter ever, and that over 40 companies were licensed by WDC, including Rockwell, Seiko, Ricoh, ITT, and Swatch.

Quoting from the Commodore Knowledge Base, the idea behind the 6800 was to create a single-chip version of the multi-chip PDP-8. While that project was going on, DEC introduced the PDP-11, which was more powerful. The 6800 guys wanted to pursue changes to the 6800 to make it more powerful but Motorola said no.

So now you can see the path here. Mensch and his team leaves to create the processor they want, and they create two versions -- the 6501 which was pin-compatible with the 6800, and the 6502, which was not. The 6501 had a 20% price advantage over the 6800 and was pin-compatible...a win-win for wooing designers to the new chip company.

Of course, Motorola got their shorts in a twist since it was (1) the developers of the 6800 (2) leaving Motorola to create (3) a pin-compatible processor (4) for 20% less. Motorola and MOS settled out-of-court, with part of the settlement being that MOS would kill the (sacrificial, IMHO) 6501 if Motorola let them continue with the 6502.

One of the other designers who worked on both the 6800 and 650x projects was Chuck Peddle.

_________________
Rich Cini
Build Master and maintainer of the Altair32 Emulation project
http://cini.classiccmp.org
http://altair32.classiccmp.org

Great info!

I have a 6501 and have not seen much info about it. It's interesting to learn about some of its background.

I did some searching for likely patents, I'll post them here for posterity.

(Of course it isn't in WDC's interests to make it easy to know which patents they might use to defend their business.)

The patent search sites are a bit weak on name searches: you don't always get all the results you'd expect.

See Bill Mensch's various patents:

http://www.patentstorm.us/inventors-pat ... 414/1.html
http://www.patentstorm.us/inventors-pat ... 887/1.html
http://www.patentstorm.us/inventors-pat ... 561/1.html
http://www.patentstorm.us/inventors-pat ... 477/1.html

see also Chuck Peddle etc etc
http://www.patentstorm.us/inventors-pat ... 563/1.html

Here's a non-exhaustive list in an arbitrary order. There's often some interesting design notes buried within.

6052792 Power management and program execution location management system for CMOS microcomputer

A monitor program stored in a ROM of a microcomputer chip of a computer is operated both to (1) save power by disabling all external buses, turning off power to a communication port, deselecting all external memory devices, and turning off a fast clock os... 04/18/2000

5737613 Method of operating microcomputer to minimize power dissipation while accessing slow memory

A method of operating a CMOS microcomputer to minimize power dissipation while accessing a plurality of memories including a first memory operable at a first frequency, a second memory operable at a lower second frequency, including operating the entire C... 04/07/1998

5511209 Programmable microcomputer oscillator circuitry with synchronized fast and slow clock output signal

A CMOS integrated circuit microcomputer is switchable under software control between high speed, high power operation and low speed, low power operation. The microcomputer includes asynchronous fast and slow clock oscillators. A synchronizing circuit coup... 04/23/1996

5438681 Topography for CMOS microcomputer

The topography of an 84 lead CMOS microcomputer chip includes first, second, third, and fourth consecutive edges, with chip control logic being located along the upper left edge. The chip includes six multiplexed peripheral I/O port buffer circuits, a dat... 08/01/1995

5212800 Method and apparatus for sensing trinary logic states in a microcomputer using bus holding circuits

A CMOS integrated circuit microcomputer system includes circuitry for sensing trinary logic states by using a tri-state driver circuit connected to both the input and output of a binary latch having only two states, both of which produce a high output imp... 05/18/1993

5123107 Topography of CMOS microcomputer integrated circuit chip including core processor and memory, priority, and I/O interface circuitry coupled thereto

The topography of a CMOS microcomputer chip includes first, second, third, and fourth consecutive edges, with chip control logic being located along the upper left edge. Five peripheral I/O port buffer circuits are located around the edge of the periphery... 06/16/1992

4876639 Method and circuitry for causing sixteen bit microprocessor to execute eight bit op codes to produce either internal sixteen bit operation or internal eight bit operation in accordance with an emulation bit

A sixteen bit microprocessor includes an emulation bit that is loaded into an instruction register with 8 bit op codes. If the emulation bit is a "1", the 16 bit microprocessor operates internally as a 6502 type eight bit microprocessor, thereby emulating...

4800487 Topography of integrated circuit including a microprocessor

The topography of a CMOS microprocessor chip includes address buffer circuitry along the bottom and lower left hand edges of the chip, data bus buffers disposed along the lower right hand edge of the chip, address register circuitry and an arithmetic logi... 01/24/1989

4739475 Topography for sixteen bit CMOS microprocessor with eight bit emulation and abort capability

The topography of a sixteen bit CMOS microprocessor chip including circuitry for enabling it to emulate, under software control, a prior art 6502 microprocessor includes an N-channel minterm logic section including 498 "vertical" diffused minterm lines ac... 04/19/1988

4652992 Topography of integrated circuit CMOS microprocessor chip

The topography of a CMOS microprocessor chip includes address buffer circuitry along the bottom and lower left hand edges of the chip, data bus buffers disposed along the lower right hand edge of the chip, address register circuitry and an arithmetic logi... 03/24/1987

3968478 Chip topography for MOS interface circuit

The chip architecture of an MOS peripheral interface adaptor chip includes data bus buffers arranged along one edge of the chip, peripheral interface buffers arranged along an opposite e

5097413 Abort circuitry for microprocessor

An abort circuit for a microprocessor includes a circuit receiving and latching an external abort signal to produce an internal abort signal, and circuitry responsive to the internal abort signal for preventing register transfer circuitry from responding ... 03/17/1992

4263650 Digital data processing system with interface adaptor having programmable, monitorable control register therein

A digital system including a plurality of metal-oxide-semiconductor (MOS) chip random access memories (RAM), read only memories (ROM) and peripheral interface adaptors coupled to a common bidirectional data bus which is coupled to and controlled by a micr... 04/21/1981

4218740 Interface adaptor architecture

A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA. The peripheral interface adaptor includes a plurality of sys... 08/19/1980

4087855 Valid memory address enable system for a microprocessor system

A digital system includes a microprocessor coupled to a data bus and an address bus. A memory for storing data and instructions is connected to the data bus and the address bus. A peripheral device is connected to an interface adaptor. The interface adapt... 05/02/1978

4086627 Interrupt system for microprocessor system

A microprocessor system includes a microprocessor, a memory, and an interface adaptor all coupled to a data bus. The interface adaptor is coupled between the data bus and a peripheral device, such as a teleprinter. A first interrupt conductor is connected... 04/25/1978

4020472 Master slave registers for interface adaptor

An interface adaptor suitable for use in a microprocessor system includes an input register coupled to a bidirectional data bus of the microprocessor system. The interface adaptor includes a plurality of registers, including a control register and a data ... 04/26/1977

3991307 Integrated circuit microprocessor with parallel binary adder having on-the-fly correction to provide decimal results

Disclosed is an integrated circuit microprocessor with a parallel binary adder whose output can be corrected on-the-fly to provide decimal results. The correction is by logical gating which operates selectively and on-the-fly, that is, while the sum from ... 11/09/1976

Sorry it isn't terribly well formatted. There are several sites which will give you a PDF for each patent, once you have the patent number.

I claim bullshido on this one. The 6502 is architecturally _identical_ to the PDP-7 (a pure accumulator machine), right down to the distinction between the accumulator and index registers. The 6800 is substantially closer to the PDP-11, and the 6809 even more-so. And, the 68000 (the 16/32-bit CPU) is virtually identical to the PDP-11.

Back in high school physics class, in 1986-'87, we had the option to earn extra points by learning how program a PDP-8. It used punched hole tape to read data. But anyway, I am posting a remark and question because I am interested in kc5tja's statement. I've heard others say the 6809 is superior to the 6502 also, do you think so and why? From a programmer's standpoint you say the 6502 is accumulator based, how would you describe the 6809 and the 68000 in similar terms?

I only ask because I am very interested in the 68000. I've always had my eye on the 68000 series. I bought the owner's manual for the 68040 when it first came out and still have it. It's out of my league right now, but I still yearn to learn the 68000 series. Desktop PC's went in the wrong direction when they chose to follow the 8080 series architecure IMO.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

From a programmer's point of view the 6809 is somewhere between the 6502, the 65816 and the 68000. It is accumulator based like the 6502 and can natively do 16 bit arithmetic and indexing like the 65816, but its very orthogonal addressing modes and the use of two stacks make it feel distinctly 68K-ish. Some common instructions use more clocks than the 6502 equivalents, but that's usually offset by the more complex addressing modes that tend to make programs shorter. The 6809 also has native support for re-entrant and position independent code, which is IMHO cleaner than the 65816's. It also "fixes" my pet peeve with the 65816 by having separate opcodes for 8 and 16 bit loads and stores, as opposed to the 65816's mode bit that makes the same opcodes handle 8 or 16 bit data depending on whether it's set or cleared.

When it comes to availability, I believe that one cannot find CMOS 6809s (produced by Hitachi as 6309s) any more. NMOS versions are still being manufactured by NTE, but only in the 1MHz speed grade. The 6502, on the other hand, is still being produced in a CMOS process that allows clocks over 14MHz, and costs about 1/3rd the price of what Mouser is selling NTE6809's for (then again, Mouser is selling NMOS NTE6502s for $14 a piece...)

So the 6809 was superior to the 6502 back when it first came out (and I really have no idea why WDM didn't use some of its nicer ideas when he was designing the 65816), and it is still a really great little chip. But the 6502 has moved on in the decades since, while the 6809 has remained fossilized in place.

I'd rank them about equal in terms of overall power. However, the 6809 is better suited to some types of software development (e.g., it'll be better at OO code) due to the superior orthogonality of the instruction set.



The 6809 is definitely an accumulator architecture as well, but it has greater support for register-register operations.

The 68000 is not an accumulator CPU, however; it's a dual-operand register-register architecture that also has a lot of sophisticated addressing modes.



You'll be spoiled for life once you learn 68000 assembly language.

The 68000's interrupt latency at 8MHz is 21.75 microseconds, almost as long as the 8086. Compare that to 1.25 microseconds for the 6502 at the same clock rate. (This includes time to finish an average-length instruction executing when the interrupt hits. The actual interrupt sequence is a little shorter.) This info is from benchmarks on WDC's website. Interrupt performance is extremely important in my use.

Other than in interrupt latency, the performance benchmarks are not much different between the 65816 and the 68000.

The PDP-11 has 16-bit registers, and the 68000 has 32-bit registers.
It's sort of a very long stretch to call them "virtually identical" for that reason alone. IMHO it's more accurate to describe them as "similar".

The PDP-11 and the 68000 both are both general-purpose register architectures, and they are similar to many other processors in that same class. So it's not that surprising they're similar.

Toshi

The 65816 instruction set is constrained by the backwards compatibility with the 6502. My guess is there weren't enough unallocated opcodes to duplicate all the 8-bit instruction as 16-bit instructions along with the new instructions. So a decision was made to have the 8 bit instructions do double-duty as 16-bit instructions.

Toshi

Register width, alone, is not enough to classify their respective architectures so distinctly as to warrant a rebuttal here, in my opinion. Architecture is architecture; register width is but a trivial implementation detail.



Of course, this is true, because the PDP-11 defined that class. The 68000 borrowed heavily from the PDP-11's architecture.

Doubtful -- I think it was the intention of the design from day one to have an M/X operand size bit in the process flags. It greatly simplifies the instruction decoding PAL. Having explicit instructions (with the 6502's existing opcode layout to remain compatible with) would have increased the size of the PAL by a factor of five.