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J64C
PostPosted: Sat Oct 02, 2021 11:11 am 
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Nice! These look very cool!
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barrym95838
PostPosted: Sat Oct 02, 2021 3:39 pm 
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BDD, within your impressive set of skills I would have to say that photography resides rather low on that list. :wink:

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BigDumbDinosaur
PostPosted: Sat Oct 02, 2021 7:30 pm 
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barrym95838 wrote:
BDD, within your impressive set of skills I would have to say that photography resides rather low on that list. :wink:

I must say it isn't something on which I've focused much. :D

I always seem to have problems with glare coming off PCBs when I photograph them.

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BigDumbDinosaur
PostPosted: Sun Jun 26, 2022 9:49 am 
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This project has languished, but I’ve gotten back on it and have made some progress. Preliminary testing has been done, I have proper resets, and the clock signals look to be okay. Also, I manually tested the IRQ circuits and they seem to be okay as well.

Next step is to prepare a glue logic CPLD and a NOP ROM to see if the logic is correct. I’ll likely be putting my crude clock stepper to work on that aspect of the testing. However, I’ve given some thought to designing and building a more elegant clock stepper that plugs into the oscillator socket with a short umbilical cord. The current unit piggybacks onto the socket, which is not the best arrangement.

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BigDumbDinosaur
PostPosted: Thu Jun 30, 2022 6:38 am 
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BigDumbDinosaur wrote:
I’ll likely be putting my crude clock stepper to work on that aspect of the testing. However, I’ve given some thought to designing and building a more elegant clock stepper that plugs into the oscillator socket with a short umbilical cord.

Shortly after I posted the above, I decided to design the “more elegant” clock stepper. PCBs are on the way. Since JLCPCB’s minimum order size is five pieces, I can make more than one of these should anyone be interested.

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BigDumbDinosaur
PostPosted: Thu Jul 14, 2022 8:22 pm 
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BigDumbDinosaur wrote:
I’ll likely be putting my crude clock stepper to work on that aspect of the testing. However, I’ve given some thought to designing and building a more elegant clock stepper that plugs into the oscillator socket with a short umbilical cord.

The new and improved clock stepper has been built and actually works.

Attachment:
File comment: Clock Single-Stepper Assembly
single_stepper01.jpg
single_stepper01.jpg [ 1.27 MiB | Viewed 880 times ]
Attachment:
File comment: Clock Single-Stepper Detail
single_stepper02.jpg
single_stepper02.jpg [ 1.77 MiB | Viewed 880 times ]
Attachment:
File comment: Clock Single-Stepper Wiring
single_stepper03.jpg
single_stepper03.jpg [ 777.43 KiB | Viewed 880 times ]

If anyone is interested in acquiring one please PM me. I've got enough parts to build four more.

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BigDumbDinosaur
PostPosted: Sun Jul 17, 2022 10:06 am 
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I've completed the first stage of testing V2.0, using a NOP ROM and observing some key signals with the logic analyzer. The unit appears to be functional running on a 1 MHz clock. Here's a capture from the logic analyzer:

Attachment:
v2_nop_test.jpg
v2_nop_test.jpg [ 336.14 KiB | Viewed 826 times ]

Signals in the capture are as follows:

  • GCLK — global clock, running at 1 MHz, which is 1/2 the speed of the clock oscillator.
  • PHI2 — Ø2, nominally GCLK, except when stretched.
  • /RD — read data control signal.
  • DATA — composite view of the data bus on the MPU side of the bus transceiver, with the bit pattern displayed as hex.
  • D7-D0 — individual data bus lines on the MPU side of the bus transceiver.

Next step will be to crank up the clock speed and see what happens with the timing. The fastest oscillator I have is 40 MHz.

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BigDumbDinosaur
PostPosted: Mon Jul 18, 2022 8:31 am 
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BigDumbDinosaur wrote:
I've completed the first stage of testing V2.0, using a NOP ROM and observing some key signals with the logic analyzer...Next step will be to crank up the clock speed and see what happens with the timing. The fastest oscillator I have is 40 MHz.

Higher-speed testing is done. The maximum speed at which the unit can reliably run is 16 MHz, which is also the limit for POC V1.3—and for the same reason.

Below is a capture from the logic analyzer while V2.0 was running at 16 MHz with the NOP ROM:

Attachment:
v2_nop_test_hs.jpg
v2_nop_test_hs.jpg [ 3.22 MiB | Viewed 783 times ]

A key takeaway from the above is while my clock-stretching setup does work, it falters at high clock speeds. The choke point is the time required for the 74AC109 J-K flip-flop to start a wait-state cycle when gated by the CPLD.

Before any wait-state setup can be carried out by the CPLD, the 65C816 has to emit a valid address, the timing of which is defined as tADS. tADS is officially specified to be 30ns maximum at 5 volts, which makes no sense—16 MHz operation would be impossible with such a figure (N.B., POC V1.2 runs with ease at 20 MHz, which gives the MPU less that 25ns to emit an address after the fall of Ø2). Judging by the time that elapsed from the fall of Ø2 to the asserting of wait-state enable (/WSE), which is 22ns, tADS is probably around 15ns, since the prop time of the CPLD causes an approximate 7ns lag after the address goes valid before /WSE can be asserted.

With a clock half-cycle period of 31ns, the 22ns it takes for /WSE to assert after the fall of GCLK (global clock) leaves only 9ns to gate the AC109 J-K flop. The AC109 requires about 5ns minimum setup time on the /K input before GCLK goes high. That requirement is being met with 4ns (worst case) to spare, so the circuit will work reliably at 16 MHz. At 20 MHz, there would only be 3ns to gate /K. GCLK will have gone high before the required 5ns setup time has been met and the AC109 will fail to start its timing cycle. So the wait-state will never happen at 20 MHz and the system will puke.

A logical modification to get around this clock calamity would be to eliminate the AC109 (and the prop time it inserts) and have the CPLD directly control the AC74 clock generator flop’s PRE input. In order to do so, I'd have to synthesize a J-K flop in the CPLD. That flop would drive the /WSE signal, which would be wired to PRE on the AC74.

The AC74 has a setup time for PRE that is defined as tPLH, which is the time that will elapse after /PRE has been driven low before Q will go high and /Q will go low. tPLH is about 11ns maximum, which is workable at 20 MHz. tPLH added to the 7.5ns pin-to-pin prop time of the CPLD, plus about 2ns for feedback delay associated with the synthetic J-K flop, means the worst-case timing would be ~20ns from the rise of GCLK to the AC74 responding to PRE and freezing Ø2 in the high state. That leaves 5ns of timing headroom at 20 MHz.

Meanwhile, since the unit can run NOPs without any problem, the next step will be to use another diagnostic ROM that bangs away at RAM, and a third one that beats on the I/O hardware. Assuming that testing is good, it will be time to assemble firmware for the unit and give it a spin. POC V1.3's firmware can be reused with only memory map changes.

BTW, there are other interesting things to be seen in the above capture. That glitch on /WSE is perplexing, although harmless.

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plasmo
PostPosted: Mon Jul 18, 2022 12:15 pm 
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Since you already have a CPLD, you should be able to place the discrete flip flops inside the CPLD to reduce propagation delays.
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akohlbecker
PostPosted: Mon Jul 18, 2022 1:45 pm 
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BigDumbDinosaur wrote:
BigDumbDinosaur wrote:
I’ll likely be putting my crude clock stepper to work on that aspect of the testing. However, I’ve given some thought to designing and building a more elegant clock stepper that plugs into the oscillator socket with a short umbilical cord.

The new and improved clock stepper has been built and actually works.

Attachment:
single_stepper01.jpg
Attachment:
single_stepper02.jpg
Attachment:
single_stepper03.jpg

If anyone is interested in acquiring one please PM me. I've got enough parts to build four more.


This is a small cosmetic detail, but you can usually fit JLC's order number under chips, so it is invisible in the final product

BigDumbDinosaur wrote:
BigDumbDinosaur wrote:
I've completed the first stage of testing V2.0, using a NOP ROM and observing some key signals with the logic analyzer...Next step will be to crank up the clock speed and see what happens with the timing. The fastest oscillator I have is 40 MHz.

Higher-speed testing is done. The maximum speed at which the unit can reliably run is 16 MHz, which is also the limit for POC V1.3—and for the same reason.

Below is a capture from the logic analyzer while V2.0 was running at 16 MHz with the NOP ROM:

Attachment:
v2_nop_test_hs.jpg

A key takeaway from the above is while my clock-stretching setup does work, it falters at high clock speeds. The choke point is the time required for the 74AC109 J-K flip-flop to start a wait-state cycle when gated by the CPLD.

Before any wait-state setup can be carried out by the CPLD, the 65C816 has to emit a valid address, the timing of which is defined as tADS. tADS is officially specified to be 30ns maximum at 5 volts, which makes no sense—16 MHz operation would be impossible with such a figure (N.B., POC V1.2 runs with ease at 20 MHz, which gives the MPU less that 25ns to emit an address after the fall of Ø2). Judging by the time that elapsed from the fall of Ø2 to the asserting of wait-state enable (/WSE), which is 22ns, tADS is probably around 15ns, since the prop time of the CPLD causes an approximate 7ns lag after the address goes valid before /WSE can be asserted.

With a clock half-cycle period of 31ns, the 22ns it takes for /WSE to assert after the fall of GCLK (global clock) leaves only 9ns to gate the AC109 J-K flop. The AC109 requires about 5ns minimum setup time on the /K input before GCLK goes high. That requirement is being met with 4ns (worst case) to spare, so the circuit will work reliably at 16 MHz. At 20 MHz, there would only be 3ns to gate /K. GCLK will have gone high before the required 5ns setup time has been met and the AC109 will fail to start its timing cycle. So the wait-state will never happen at 20 MHz and the system will puke.

A logical modification to get around this clock calamity would be to eliminate the AC109 (and the prop time it inserts) and have the CPLD directly control the AC74 clock generator flop’s PRE input. In order to do so, I'd have to synthesize a J-K flop in the CPLD. That flop would drive the /WSE signal, which would be wired to PRE on the AC74.

The AC74 has a setup time for PRE that is defined as tPLH, which is the time that will elapse after /PRE has been driven low before Q will go high and /Q will go low. tPLH is about 11ns maximum, which is workable at 20 MHz. tPLH added to the 7.5ns pin-to-pin prop time of the CPLD, plus about 2ns for feedback delay associated with the synthetic J-K flop, means the worst-case timing would be ~20ns from the rise of GCLK to the AC74 responding to PRE and freezing Ø2 in the high state. That leaves 5ns of timing headroom at 20 MHz.

Meanwhile, since the unit can run NOPs without any problem, the next step will be to use another diagnostic ROM that bangs away at RAM, and a third one that beats on the I/O hardware. Assuming that testing is good, it will be time to assemble firmware for the unit and give it a spin. POC V1.3's firmware can be reused with only memory map changes.

BTW, there are other interesting things to be seen in the above capture. That glitch on /WSE is perplexing, although harmless.


Interesting investigation. I really need to get myself one of those logic analyzers

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Proxy
PostPosted: Mon Jul 18, 2022 7:29 pm 
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since my SBC is using the same clock circuit (minux the JK-FF since that is in the CPLD) i would assume it to run similarly well. (PCBs and Parts are still shipping, but it shouldn't take more than a few weeks)
But i still wish i had a Logic Analyzer like that just to compare to your own measurements.

Which Analyzer are you using, and would you recommend it, or another Analyzer?
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BigDumbDinosaur
PostPosted: Mon Jul 18, 2022 8:44 pm 
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plasmo wrote:
Since you already have a CPLD, you should be able to place the discrete flip flops inside the CPLD to reduce propagation delays.

The AC109 can be synthesized in the CPLD—I mentioned that when describing a possible solution to the timing “choke point.” The AC74 needs to remain discrete because the CPLD’s output levels are TTL and can’t reach VCC × 0.8 in a 5 volt system, VCC × 0.8 being the specified minimum for the 65C816's Ø2 input. I do have pullup resistors on the outputs of the CPLD to try to get them as far into CMOS logic 1 territory as possible. However, doing so creates an R-C situation that slows the rise time once above the theoretical 3.4 volt no-load limit of a TTL output. As the 816 requires a Ø2 rise and fall time of no more than 5ns, I can’t expect such an arrangement to work in a reliable fashion.

akohlbecker wrote:
This is a small cosmetic detail, but you can usually fit JLC's order number under chips, so it is invisible in the final product

I don't mind if it’s visible and in fact, there was one occasion where I needed to refer to it.

Quote:
Interesting investigation. I really need to get myself one of those logic analyzers

I got along without one for many years and in fact, debugged numerous digital designs using only a logic probe and scope. However, after building POC V1.2, I wanted to do some in-depth circuit analysis, which meant having to simultaneously observe numerous signals. So I decided it was time to make the investment.

Proxy wrote:
since my SBC is using the same clock circuit (minux the JK-FF since that is in the CPLD) i would assume it to run similarly well. (PCBs and Parts are still shipping, but it shouldn't take more than a few weeks)
But i still wish i had a Logic Analyzer like that just to compare to your own measurements.

It would be interesting to compare notes. :D

Quote:
Which Analyzer are you using, and would you recommend it, or another Analyzer?

Here’s the one I have. I recommend it with the caveat that you need a PC running MS Window$ to use it—I keep a box running XP SP3 for that and for doing mechanical and electrical drafting. The logic analyzer’s software is very flexible and handles all sorts of specialized situations.

BTW, one of the LA’s software capabilities is that of “printing” the capture display to the Windows clipboard as graphic image that can pasted into other programs. I use this feature to create annotated images like that seen above by pasting into my mechanical drafting program.

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Proxy
PostPosted: Mon Jul 18, 2022 9:41 pm 
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I only have 1 PC and it's running Windows 10 because Linux is way too much of a hassle for me to be using it as a daily driver/gaming PC.

and for the probe itself, ~400 USD is a hefty price but i can see it being very worth it for the bandwidth and obvious ability to look at many many signals at once.
but sadly their site only accepts credit cards, and i don't have one... so that won't be happening.
well guess i'll have to find one the old fashioned way, googling around and reading reviews.
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BigDumbDinosaur
PostPosted: Tue Jul 19, 2022 1:55 am 
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Proxy wrote:
and for the probe itself, ~400 USD is a hefty price but i can see it being very worth it for the bandwidth and obvious ability to look at many many signals at once.

Actually, $400 is quite reasonable when compared to the units sold by Agilent, Rigol and others. I had looked at a refurbished Agilent with 16 channels. It was going for $950.

Quote:
but sadly their site only accepts credit cards, and i don't have one... so that won't be happening.
well guess i'll have to find one the old fashioned way, googling around and reading reviews.

They do accept Paypal. I found this on their ordering web page:

    If you'd rather FAX your order, or if you wish to pay by bank wire transfer (TT) or by PayPal, please print and submit our FAX order form.

Also, they have a German distributor.

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Proxy
PostPosted: Tue Jul 19, 2022 6:22 am 
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BigDumbDinosaur wrote:
Actually, $400 is quite reasonable when compared to the units sold by Agilent, Rigol and others. I had looked at a refurbished Agilent with 16 channels. It was going for $950.

oh wow, didn't expect LA's to be that expensive!
BigDumbDinosaur wrote:
They do accept Paypal. I found this on their ordering web page:

    If you'd rather FAX your order, or if you wish to pay by bank wire transfer (TT) or by PayPal, please print and submit our FAX order form.

Also, they have a German distributor.

So i would need a FAX to use paypal (I don't even have a landline phone), why couldn't they just include that in the online shop directly?

also that alternative distributor says during checkout that they only ship to business in the EU, not individual people.
I appreciate you trying to help me but i don't think this will work out, i'll just cut my losses and look for some other piece of hardware.
Plus i do still have my 4 channel Oscilloscope, so i will atleast be able to look at the clock circuit all at once to see if that is working correctly.
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