In my quest to learn the inner workings of the 6502, I developed a near gate-level simulator
in Verilog which you can find at: https://github.com/klynch71/6502sim

It is based on the Hanson block diagram and the netlist of the Visual6502.org project.
All of the internal control signals are named and represented.

The simulator is not intended for synthesis but rather to learn and observe the
actual inner workings of the 6502. A program can be run and the output can be viewed using GTKWave.

The Timing Generator block turned out to be simple. The Random Control Logic block....not so much.

--Kevin

Nice one, thanks for sharing (and MIT-licensed too, that's great.) And welcome.

I suppose it will take an age to run a testsuite like Klaus Dormann's?

Could you say a few words on how you've dealt with electrical situations like the precharge and the directional bus switches?

Thanks.

>I suppose it will take an age to run a testsuite like Klaus Dormann's?

Pretty much. Here are some stats on my machine, a MacBook Air M1:
- runs at about 1.3kHz
- 32 seconds to run through the first 40 tests of Klaus's program. This is up to but not including the full binary add/subtract test.
- about 4 minutes for each complete loop of the binary add/subtract test. A loop being 0-255 added to and subtracted from another number
with all checks.
- 75 seconds per loop of Bruce Clark's decimal test.

>Could you say a few words on how you've dealt with electrical situations like the precharge and the directional bus switches?

The precharge mosfets serve as pullups so I just used the Verilog pullup() primitive.
Similarly, the directional bus switches are tranceivers so I used the Verilog tranif1() primitive.
My primary interest was for the control signals.

Ah, thanks - I hadn't realised verilog would be quite so amenable. Great!