I've been adding some additional function to the BIOS update, now supports multiple sector reads, writes and verifies... it also enables the write cache on the Microdrive when it's initialized.

Testing so far has been solid and reliable, albeit not a ton of hours and only a single prototype system. Still, it's promising as there hasn't been any crashes (yet). Doing block reads always had good performance, as the Read Ahead Cache is enabled by default on the drive. In general, the MicroDrive tends to perform a bit better than a Compact Flash Card on single sector reads. As the Write Cache is not enabled by default, write performance with single block writes was pretty bad, under 30KB per second. This is due to the disk latency and the suspected sector interleave, which is not listed in any spec sheet I've managed to dig up. As the prototype system is only running at 4 MHz, it's just not quick enough to request block writes without missing the next block address, and having to wait for the disc to complete a revolution to write the next sequential sector. Enabling the write cache during the initialization process put the write data rate right up with the read data rates... nice.

Using my earlier testing of single block transfers, the data rates are around 176KB/second (read and write are virtually the same). Using a modified routine with the new BIOS to use 16KB transfers (32 blocks per transfer) and the rates go up to 183KB/second. A nice increase overall. But alas... there's no defacto OS and filesystem on the 6502 that would be managing multiple sector transfers, especially with a 64KB address range.

My next phase is to build a daughter board for the C02 Pocket SBC, which will include the SC28L92 DUART, a 128KB SRAM, a 128KB NOR Flash (replacing the EEPROM) and an ATF1504ASV CPLD. The goal is to replace both the existing ATF22V10 and ATF16V8 used for all of the existing glue logic on the two boards. I'll use a small ribbon cable from the daughter board to the RTC/CF-Card adapter plugged into the ATF16V8 socket. Working on that now.. but will be a while before that's done, as I need to figure out the CPLD code and pin-outs first.

_________________
Regards, KM
https://github.com/floobydust

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Agreed, I added the multiple sector transfer as more of a luxury... and of course, it might come in handy at a future time with a different OS/Filesystem. As DOS/65 is basically a port of CP/M to the 6502, it' based on 128 byte sector sizes, so 4 sectors per single 512 block on the IDE device. I have a single 512 byte block buffer allocated for this, and the SIM module calls BIOS with single block transfers only. The 16KB transfer block size was just an arbitrary size for performance testing and not related to anything filesystem related.

The code base should be fairly tight, as I basically made some changes/updates to my existing BIOS that was running the CF Card in True IDE mode.

The BIOS, now at an initial version of 4.00, supports both serial ports (and Timer) for the SC28L92, the DS1511 RTC and an IDE interface with 16-bit data transfers. Working within 1.75KB of EEPROM space, I've got 33 bytes free. Granted I've allocated another 96 bytes of the I/O page ($FE00) for vector and configuration data, where most of it is moved to low RAM during system initialization. So far, so good... more testing to do.

_________________
Regards, KM
https://github.com/floobydust

I've recently spent some additional time working on the 3.3V system... some fine tuning and cleanup of the BIOS and Monitor, a few more improvements to DOS/65 to work with it and a decent version of a setup utility that will allow setting of the DS15x1 RTC and some decent testing and such of the Hitachi MicroDrive. The tests should work with any IDE device, but the utility does rely on the C02BIOS routines for accessing the MicroDrive and some Monitor routines as well.

I've also done some read and write benchmark tests and the results are quite good. The updated utility has a 16MB sequential read and write benchmark test. It's more flexible than the earlier one for the CF Card. It allows a starting block (LBA) for both tests, so you don't have to overwrite the start of the device. The updated C02BIOS also supports multiple block transfers (CF Cards don't support multiple block xfers) and it also enables the Write caching on the MicroDrive.

Referencing an old post here: viewtopic.php?f=4&t=6223&start=15#p81954

The best read performance I was able to get with a CF Card was 326KB/Second.
The best write performance I was able to get with a CF Card was 278KB/Second.

NOTE: The above speeds were NOT the same CF Card, so the figures aren't completely realistic.

The MicroDrive exceeds these figures:

Read performance is generally between 360KB/Second to 365KB/Second
Write performance pretty consistent at 320KB/Second.

It's also very good performance when you consider it's a slower rotational speed at 3600RPM (average latency is 8.33ms) and you also have to factor in seek times as well. Still, the MicroDrive outperforms the CF Cards with PIO Mode 4.

I'm hoping to get the CPU speed up around 16MHz with the final hardware design and be able to step the CPU speed down to 8MHz when accessing the I/O devices.

I'm quite happy with the implementation so far. The 6GB drives are readily available as NOS for about $20 each. The source I found noted he had around 80 drives.

I've also decided on using an Altera CPLD for the next SBC... and try to squeeze a fair amount into it:
- The usual I/O decoding and generating read and write signals
- A two-speed CPU clock for 16MHz and 8MHz
- An I/O bus setup that also has 16 data lines (for the MicroDrive)
- A paged memory mechanism similar to Sergey's Zeta SBC V2 (which is compatible with Fuzix)

I managed to score a new Altera USB Blaster Rev c for $30... some new EPM240T100 CPLDs and have a Win7 VM running Quartus 13.0 sp1. Everything is working... so now on to more fun... it's going to be awhile... new toys, new learning.

I'll post some updated code to my GitHub page with the cobbled up schematics for the 3.3V system... hopefully in the next day or two.

_________________
Regards, KM
https://github.com/floobydust