Did you have a look at the visual 6502 schematics to maybe see how the 6502 does phi2 generation? Maybe that gives a hint eg how phi0, phi1 and phi2 are related and how they are generated and used?

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

That sounds like a great idea. However, I have not done this and, after having a quick look at visual6502.org, I am not even sure where to start with doing such a thing. Any hints?

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Curt J. Sampson - github.com/0cjs

I believe if you click on a pin it highlights the whole net so you can see where it goes and what it interacts with. I'd expect phi0 to just go into a pair of NAND or NOR gates to generate the two phase clock signals, which are then probably used elsewhere and also buffered on the way out of the IC.

Yes indeed, with a little practice you can click and pan to explore the circuit.

There's a snippet of the original blueprint here which relates to clocks:
https://web.archive.org/web/20200624185 ... 2_and_6504

Yes, I see that in the simulator one can click on a pin and it lights up some stuff. But what's getting lit up is not very readable to me; the transistors are certainly not regular schematic symbols there. It doesn't help that none of the pins are labeled, either.

The blueprint fragment looked a lot more comprehensible, but still rather beyond my detailed comprehension.

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Curt J. Sampson - github.com/0cjs

I can provide more by way of blueprint fragments, but always with the disadvantage that you'll see transistors and have to figure out the logic gates for yourself. Which is quite easy, so I recommend you give it a go.

Right. Figuring out gates from transistors can't be that hard, can it? Is there a tutorial on this stuff somewhere?

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Curt J. Sampson - github.com/0cjs

All you really need to know is that a pullup has a number of pulldowns connected to it. Each pullup is a logic gate, and if it has one pulldown it's an inverter. Two in series makes a NAND, two in parallel makes it a NOR. There's also a superinverter... I'm sure there's a picture somewhere of an NMOS superinverter... ah yes, see https://www.pastraiser.com/technology/n ... gates.html for all the info you need!

Ah, yes; that makes that bit a lot more clear. However, I'm still having problems relating this to the image in the Visual6502 simulation. It seems to me the blueprints would be a much better way to go, but despite the blueprints page you showed me mentioning something about reverse-engineered blueprints, I can't find any.

Overall, I seem to be missing a huge amount of background necessary to pursue this. Could you perhaps just walk through the first half dozen places the clock input on pin 37 goes to, step by step, showing me what you're referring to at each step so I can get a better idea of how to do this? Right now I feel kind of like a software guy who's never touched hardware might feel if you said to him, "Just look at the inputs to and outputs from the '138 and you'll have a memory map of the system." Yeah, dead easy to figure out if you're familiar with address decoding, but a completely mystery where you won't even know where to start until someone points you at a specific page on the Wilson Mines site.

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Curt J. Sampson - github.com/0cjs

It's true that reading NMOS layout shapes is another skill again - not unmasterable but quite a big step.

As for the schematics, here are a few crops from the blueprints, as kindly scanned by Donald Hanson and shared with the following agreed attribution: "(Credit: crops from MOS Technology Sheet 2 "650X-C Logic Diagram Microprocessor" "Engineering Approval by ORGILL, MENSCH" dated 8-12-75, Scan: Courtesy of Donald F. Hanson, Dept. of Elec. Engr., Univ. of Mississippi)."

These are all from the north edge and relate to the clock pins. See also the crop previously linked on the wiki page - that's an archive link because the original is unfortunately offline at present.

Sorry this is a bit of a jigsaw puzzle, but the original scans are not freely redistributable. It would be a good thing for someone to draw out what's going on here: 3 pads, 2 on chip clocks, and metallisation options to allow either 6501 or 6502 usage of the pads.

The circuitry under (to the south of) pad 37, as seen on the wiki page, shows a NOR gate, which presumably was sufficient to make the on chip clocks non-overlapping.

Well, between being able to see only small excerpts of the MOS 6502 schematics, my poor skills at reading them and the Visual 6502 Wiki being down it seems I'm not going to get much out of those unless someone else wants to supply some help. However, I did see a mention of on this archived wiki page of a "Giant Schematic" which I eventually found here and have also attached to this message with a slightly clarified name. My understanding from the page above is that this is a Rockwell 6502 schematic and the title in the upper right corner, "R6502," seems consistent with that. It's at least NMOS, so I would imagine should not be too far from MOS behaviour.

The part of the circuit relating to the three clock pins is down in the lower right corner and seems exceedingly simple:


If I'm reading this right the ϕ0 input seems to go through very minimal processing before becoming the chip clock signal which is also directly output to ϕ2. I would guess there that there is going to be a tiny bit of delay on the output, but not enough to cause any issues with using ϕ0 instead of ϕ2 to clock things. But I'm not clear what's going on then with the slow rising edge I'm getting out of the CPU I captured near the top of the thread, which is marked as an R6502 (but might be some other chip, though it's definitely NMOS from the power consumption).

Is the schematic above basically the same as the MOS schematics that have been posted to this thread?

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Curt J. Sampson - github.com/0cjs

Hi Curt, good idea to look at Balazs' giant schematic. There's a pretty good chance it matches the MOS blueprints - but I have a bad head today and can't do the necessary investigation.

As for the slow rising edges, it's a typical problem of NMOS technology that it's difficult to get a fast pullup, so I think what you saw there is very likely just indicative of that. The crucial voltage of the on-chip clock will be down near 1v, and certainly below 2v, as that's when pass transistors will turn on. The remainder of the rising edge being quite slow won't have much effect, I think.

To my eyes, the bottom diagram ("phi2 off") matches the top left four transistors in your diagram plus the three just to the right of them, but the ones to the far right on your diagram aren't on the hand-drawn one. Note that it shows a connection to "phi1 chip" that connects to the rest of your diagram. Your one is missing the resistor to VCC, which would explain the slow rise time on ph2out (which is something I've observed in an NMOS 6502 in the past as well, so I don't think it's unusual).

The bit missing to the right of the cropped diagram is just an inverting buffer - it may actually be just on the right hand side of the first diagram BigEd posted, slightly cropped off the edge.

I'm having more trouble corresponding the phi1 side of things between your diagram and the hand-drawn ones. The hand-drawn ones seem to have a lot more buffering in them.

So in your diagram then, looking at what it actually does - the three transistors in the top right form an inverter from p0 (with one of them just being there to protect against static discharge or out-of-range input voltage I think). The three transistors down an left from that are very important - they form a NOR gate, NORing this inverted phi2in with phi1. This ensures that phi1 and phi2out are non-overlapping - they'll never be high at the same time. Effectively phi2's rising edge will get delayed until phi1 has settled low.

Then the four transistors in the top left just invert that signal twice, with totem pole inverters, which will buffer it I guess before it gets used in a lot of places on the chip.

The phi1 side is simpler - inverted p0 is re-inverted, then inverted again, and then fed through two more totem pole inverters before going out to the rest of the chip and the outside world.

The top diagram in BigEd's post does the same as this but re-inverts another two times. It's possible that they originally designed it that way, but then took out the extra two inverter stages; or the diagram you found was just simplified a bit.

Edit: taking a second look, the middle hand-drawn diagram in BigEd's post does match the lower half of the diagram in your post. I'm not sure what the top diagram in BigEd's post is about.