Hello there,

I have a SBC with a 6522 and a 6850 connected as follow :





So the CB1 output of the 6522 act as RXClock and TXClock for the 6850 and fix the baud rate.

Reading the datasheet it seems to me that I have to use the SR Mode 4 on the 6522 to do that... Is that right ?

If Yes how should I initialize the 6522, how can I fix the baud rate and is the port B still usable as parallel port for other topics ?

Thanks for help. Regards.
Philippe

I haven't used mode 4 but my datasheet seems to imply that it does not send shift clock pulses on CB1, only data on CB2. Mode 5 sends both. The disadvantage of mode 5 is that you need to keep writing bytes to the SR in order to make it keep sending clock pulses, or it will stop after 8 and wait for you to provide more data.

You could consider using mode 4 and CB2 and writing alternating bits ($55 or $AA) into the shift out register. It will then repeatedly send those bits through CB2 at the rate chosen by timer 2, without you needing to interact with it further, I believe.

None of this affects port B, it's still available for use - you just won't be able to use the handshaking associated with it.

Edit: I'm actually doubtful this is correct though because shifting out data without sending a clock signal is pretty pointless! So it's worth trying mode 4.

All I'd expect you to need to do is set the shift register mode up in the ACR (e.g. set it to 16 for mode 4), set the two T2 registers to define how slow you want your clock to be, relative to the system clock, and maybe do a dummy write to the SR to kick things off. I haven't done this myself but it's worth just trying I think.

_________________
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The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Hello there,

I have a question for the assembly language specialists.

Below we see the 6809 (I know, its a 6502 forum...) code on the right and the timing diagram of the data bus on the left.





Can somebody confirm that the data which is read in the 6850 by the instruction "LDB ,X" is indeed $0C ?
We can clearly see $E684 then a $C5 (what is that ?) then $0C (the data read at address X ???) then we see the $C502 of the operation "BITB # $ 02"?

If the data is really $0C logically the program switch to END and the loop starts again and nothing is ever written in the output register of the 6850 ...

Finally if anyone has any idea why the TDRE bit of the 6850 is not to one after a reset that interests me a lot ??? Could that come because the CTS input (coming via a MC1489 line receiver) is floating ?

Have a good evening.
Philippe

Yes, it looks that way to me.

Many 6809 instructions take more cycles than you'd expect -- they include extra "internal operation" cycles which make no meaningful use of the bus. 65xx processors do this, too, but not nearly as often.

In this case it seems the CPU fetched the E6 84 but needed an extra cycle to decode what that means. So, it went ahead and kept fetching, which is why it got the C5 from the following instruction. Then it figured out what "E6 84" means and fetched the data (0C) for the first instruction. So, ...

The E6 84 executed with one extra bus cycle.
The C5 02 executed without any extra bus cycles.
The 27 04 executed with one extra bus cycle (and IDK where the 00 came from).
Then we have the 7E F8 1E.

Sorry I can't advise you regarding the TDRE bit on the 6850.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Yeah, but we're all Motorola-bus friends here, and it's not like 6502 folks don't use 68xx parts left and right. (Sometimes changing the number to 65xx. :-))


Last time I was looking at cycle-by-cycle bus timing I found it very useful to break things down further than instructions and chart out the individual bus cycles to be taken for each instruction, as you can see in the table in that link. You need to do this to make sure you know on which cycle something's actually being read, as Dr.Jefyll points out above.

The original 6502 programmer's manual helpfully includes cycle-by-cyle breakdowns of each instruction type in an appendix. I don't recall off-hand if my 6800 manual had the same, but at the very least it gives the number of cycles taken for each instruction and you can usually work out from that where at least some of the cycles will be, and then know at least approximately where the "dead" cycles should be.

_________________
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Hello,

With cts and rts connected together and dcd to +12 V (logic 0) everything work fine !

Thanks all for your advices !

Regards.
Philippe