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Procrastin8
 Post subject: SC28L92A1A source
PostPosted: Wed Aug 11, 2021 12:33 pm 
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With the global chip shortage, I've seen the prices of these double over the last 6 months. Does anyone have a good source of these? €12 plus shipping to europe is rather steep at the moment when they were less than €8 very recently. But maybe i'm being too cheap? I want to play with these in my 65C02 SBC.
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floobydust
 Post subject: Re: SC28L92A1A source
PostPosted: Wed Aug 11, 2021 12:45 pm 
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Keep in mind that Texas Instruments also make their version of the SC28L92 (TL28L92). Exar (now MaxLinear) also made their version of some of the NXP DUARTs as well. You might find these a bit less expensive, but they are completely code compatible with the NXP chips.

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BigDumbDinosaur
 Post subject: Re: SC28L92A1A source
PostPosted: Wed Aug 11, 2021 6:18 pm 
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floobydust wrote:
Exar (now MaxLinear) also made their version of some of the NXP DUARTs as well. You might find these a bit less expensive, but they are completely code compatible with the NXP chips.

There are some subtle differences between the genuine NXP parts and Exar equivalents. The most important of these is the Exar parts lack the I/M pin function of the 28L92, which determines if the device will run in x86 or 68K mode. The Exar equivalent of the 28L92 set up in the (recommended) x86 mode is the XR88C192. The XR68C192 would be used if 68K mode is desired.

MR0 in the XR68C192/XR88C192 has slightly different functionality from MR0 in the 28L92. If you decide to go with the Exar part be sure to thoroughly read the relevant data sheets.

Attachment:
duart_88c92_88c192.pdf [4.4 MiB]
Downloaded 37 times
Attachment:
28l92_compatibility.pdf [32.3 KiB]
Downloaded 44 times

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Procrastin8
 Post subject: Re: SC28L92A1A source
PostPosted: Thu Aug 12, 2021 6:57 am 
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floobydust wrote:
Keep in mind that Texas Instruments also make their version of the SC28L92 (TL28L92).

From what I can tell, this was never made in 44 pin PLCC package so won't suit my needs.

BigDumbDinosaur wrote:
]The Exar equivalent of the 28L92 set up in the (recommended) x86 mode is the XR88C192. The XR68C192 would be used if 68K mode is desired.

Why is x86 mode recommended? From what I've seen here on this forum about it (and the very helpful full PDF guides) this is predicated on a system already having separate and qualified R and W signals, correct? Mine does not, and I was planning on running it in 68K mode.
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BigDumbDinosaur
 Post subject: Re: SC28L92A1A source
PostPosted: Thu Aug 12, 2021 3:41 pm 
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It was brought to my attention by Dieter (ttlworks) that I've, to date, made 6501 posts. Guess what this one will be. :o

Procrastin8 wrote:
BigDumbDinosaur wrote:
The Exar equivalent of the 28L92 set up in the (recommended) x86 mode is the XR88C192. The XR68C192 would be used if 68K mode is desired.

Why is x86 mode recommended?

68K mode accommodates the Motorola 68000-style bus cycle, which is not like that of the 6502. While the 68K does have the single read/write output that corresponds to RWB of the 65C02 or 65C816, the 68K also has status outputs (/AS, UDS and VDS) that tell peripheral devices when the buses have settled and are valid. The 6502 doesn't have such outputs, which means accesses to non-65xx peripherals have to be qualified with Ø2. Failure to do so may result in register corruption during Ø2 low, when the data bus is not fully settled.

Given the lack of a "data bus is valid" signal from the 6502, your only recourse if using 68K mode is to qualify the DUART's chip select with Ø2. Doing so narrows of the selection "window" to part of the high phase of Ø2—some prop delay in the glue logic gets into the picture, so the chip select will not be seen by the DUART until some time after the rise of Ø2. The 28L92 responds faster to a read/write operation if it is already selected when the read/write commences. Achieving that isn't possible in 68K mode with the 6502, especially during a write cycle. If you desire to run your system into the double-digit clock range you'd have to wait-state the 28L92, defeating one of its strengths, which is rapid response to a chip select. Also, you'd be adding hardware to generate the wait-state.

A parallel problem with 68K mode is when the 28L92 is used with a 65C816, both read and write cycles must be fully qualified by Ø2, or a bus transceiver must be used to prevent data bus contention during Ø2 low.

Quote:
From what I've seen here on this forum about it (and the very helpful full PDF guides) this is predicated on a system already having separate and qualified R and W signals, correct? Mine does not, and I was planning on running it in 68K mode.

You still have to use some gates to qualify the DUART's chip select, so using 68K mode doesn't gain you much. The fully-qualified R/W signals required in x86 mode can be easily generated with a single 74*00 quad NAND gate (see below—three of the gates are needed). The fourth, unused gate can be pressed into service to invert the reset signal to suit the requirements of the 28L92 when in x86 mode.

Aside from the DUART, if you use asynchronous SRAM you will likely be using RAM with separate /RD and /WD control inputs. As with non-65xx I/O hardware, you never want to expose RAM to the data bus during a write cycle unless Ø2 is high. See where this is going?

Attachment:
File comment: Single-Chip, Fully-Qualified Read/Write Logic
read_write_qualify_alt.gif
read_write_qualify_alt.gif [ 46.98 KiB | Viewed 397 times ]

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