One good use of that is to use CS1 for Phi2, and /CS2 for a chip select that is directly derived from the address lines without clock
(sorry if SPI65 has phi2 already there, can't remember right now...

André

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

Additional note:

- the Micro-PET has a very simple SPI interface included (but that only runs in mode 0 and fixed clock), it has a nice feature that reading the data register triggers another byte transfer, so while you store the byte just read, the next byte is already read from the SPI. Only if you read the "peek" register you get the data without triggering another transfer. See here https://github.com/fachat/MicroPET/blob ... LD/SPI.vhd and associated documentation https://github.com/fachat/MicroPET/blob ... PLD/SPI.md

- the Micro-PET boots from SPI, with a very simple schematics: on "ipl='1'" the IPL code shifts out the Flash read command and address zero, then counts 256x8 bits to be shifted in. During shift-in, the address lines are set to high (A8-18), or fed from the IPL counter (A0-7), and set to write, while the shift register output is directly fed to the databus. So the top 256 bytes are loaded into the top of RAM - from where the CPU then boots! See basically the last 60 lines of https://github.com/fachat/MicroPET/blob ... LD/Top.vhd

So, if I have a CPLD on a board, I'll never use a parallel ROM ever again

Edit: sorry if I'm kind of (inadvertently trying to) capturing the thread, but saw this popping up when I was enthusiastic that I managed to get my boot-from-SPI working

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

hello Bill,

It looks like you captured all the logic accurately. For the clock circuit of the SO[0..7], the following can be used. I may have had problems with an XOR in the logic, so I worked around it the long way. I'm not sure which is more efficient for Altera.


It does appear that the preset and reset of the flipflops are active low, so your added inversion also looks correct.

Please report back your results when you are able to test the functions in circuit.

Thanks!

Daryl

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Hi Daryl,

Thank you for looking over the schematic. I'm please to know it is correct. Altera Quartus software will minimize the logic automatically so the gates drawn in the schematic are not necessarily implemented as is.

I do have SPI based Ethernet as well as and SD card. I'll let you know how the schematically based CPLD worked out. Using Atmel's pof2jed program I can also convert Altera's .pof file to jed file to program your ATF1504 so you can also check it out on your hardware setup.
Bill

Attached is the Quartus design files of the 65SPI that you've looked over.

I ordered a few SPI EEPROM, 25LC080, from Mouser and built a CPLD protoboard so I can use CRC65 SBC to test the 65SPI designed in Altera schematic. The CPLD prototype board already have existing pin assignment so I removed a few pins from 65SPI so they will fit. The pins removed are MRD, MWR, CS2, and 5 slave selects. It compiled OK with 75% macrocell utilization. I'm ready to write the software to test the SPI.
Bill

Awesome! I look forward to the results.

Good luck!

Daryl

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Powered up the board and no smoke!

25LC080 is a relatively slow SPI device, so instead of using external clock, I just slow down 6502 to 7.37MHz. Fixed a couple simple mistakes and I'm able to talk to 25LC080, but there is a problem: writing to SPI control is causing soft reset even though the software reset bit is 0. I believe the problem is due to data bit 7 not valid until near the falling edge of PHI2 clock. While data bit 7 is changing, it can generate glitch on the asynchronous preset of flip flop. I redesigned the SRES logic so data is latched in on the falling edge of clock and cleared on the next falling edge of clock. In attached schematic, the bottom flip flop was the original SRES logic. The top flip flop is the modified logic (note: nCLK is inverted PHI2).

With that mod, I can now change the SPI control without spurious reset. I have more tests to do...
Bill

That's good news. I added the soft reset in the move from Zilinx to Atmel. it was not really tested thoroughly. I'll have to go back and see if the Atmel version has any issues. I believe 1 person has it working in hardware.

Thanks!

Daryl

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I am able to write and read verify 25LC080 serial EEPROM with 7.37MHz 6502 CPU clock. I change 6502 CPU clock back to 14.7MHz and run the same test again. In this case SPI clock is 7.37MHz, twice the SPI speed rating of 25LC080, but it all works just fine. I guess 25LC080 SPI spec is conservative.

The reason I changed the CPU clock back to the original 14.7MHz is because I want to check whether 65SPI will run at 14.7MHz and whether the external clock feature works So I divided the 14.7MHz clock by 4 and used it as the external clock input; enable the ECE bit of the SPI Control; verify the clocking is 1.84MHz and do EEPROM write followed by read verify. All works perfectly. Yep, it is all good and I'm satisfied. Please let me know if there are anything you want me to test.
Bill

If I ever run out of projects (unlikely), I can work on this: QVGA over SPI. I have at least 3 projects ahead of it.

sorry to just burst into here like this...
but recently i've been thinking about using SPI as an expansion bus (similar to PCIe) to save on Pins required for an expansion connector. though controlling multiple /SS lines with a single SPI Master seems complicated.
anyways, the idea made me wonder how one would go about hooking up a regular 8 bit parallel device (like a Video Controller, Sound chip, etc) to an SPI Bus as a slave.
I don't know if someone else has already thought about this or even tried it...

but in my search i came across these SPI 8/16 bit GPIO Expanders. the MCP23S08 and MCP23S18. they come in a DIP package and run at 1.8V to 5V, though their SPI speed is limited to 10MHz. (maybe overclockable?)
the 8 bit version seems a bit more useful since you can put 4 of them in parallel using the same /SS line from the SPI Master, while the 16 bit one only has that option for the I2C version of the chip.

i was also thinking that the 8 bit chip could be replicated using a CPLD, allowing for potentially higher Clock Speeds and more specific features around connecting to 8 bit devices. though that would obviously drive up the total cost of the interface.

either way, any thoughts on this?

Nowaday I'm leaning more toward serial expansion as well. This is lesson-learned from overclocking of W65C02 which can easily run twice the manufacturer's max frequency of 14MHz PROVIDED the number of core devices is small to keep down the bus loads and minimize bus interconnections. Conceptually the core devices are CPU, CPLD, RAM, and dual-port RAM (video); everything else (keyboard, boot serial EPROM, GPIO, serial, I2C, SPI) are connected to CPLD serially. My feeling is a full featured W65C02 can operate at 30+Mhz in such configuration. I'm looking at Olimex's UEXT which supports I2C, SPI, and serial in a 2x5 header.

Bill

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why not combine both into a single 12 pin connector?
it would mean that both I2C and SPI Devices could share the same connector for Computers that support both SPI and I2C.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?