6502.org • View topic - Running buses off the main PCB, I/O on daughter board

View unanswered posts | View active topics

Board index » 6502.org Users Forum » Hardware

All times are UTC

Running buses off the main PCB, I/O on daughter board

Page 3 of 3

[ 32 posts ]

Go to page Previous 1, 2, 3

Previous topic | Next topic

Author

Message

BigDumbDinosaur

Post subject: Re: Running buses off the main PCB, I/O on daughter board

Posted: Sat Jul 17, 2021 12:23 am

Joined: Thu May 28, 2009 9:46 pm
Posts: 8468
Location: Midwestern USA

banedon wrote:

The reason for the GAL is decoding the I/O as there are not enough pins to do it* on the ATF1504AS. Been looking around to find an ATF1504 with a prop delay of 7.5ns along with 84 pins - all seem to be out of stock/discontinued. The only 7.5ns one I can find is 44 pin. - at least in PLCC. So it looks like I'll have to go with the 10ns one (ATF1504AS-10JU84), but I'll keep looking just in case someone has some nos (new old stock).

You could use the ATF1508AS in PLCC84, which has twice as many uncommitted I/O pins as the PLCC44 1504. As a bonus, you also get twice as many macrocells.

Quote:

By the way, those PLCC84 sockets are (naturally) huge

Yep! The SCSI host adapter I made for POC V1.1 has the PLCC84 version of the AMD 53CF94 ASIC. That one chip uses up about 40 percent of the total PCB area.

The alternative would be to go with a QFP package, but then you'd be faced with soldering a lot of fine-pitch leads. There is no free lunch with this stuff.

Quote:

* Pins required on the CPLD:
16 for D0-7 (in) & for A16-23 (out) - bank latch
2 for PHI1 & PH2 (in)
1 for RWB (in)
2 for RD & WD (out)
2 for VDA/VDP (in)
8 for A15-A8 (in) - used to determine IO and ROM select lines
3 for VIA0, VIA1 and SER select lines
2 for expansion I/O select lines
4 for RAM select lines
1 for ROM select line

VIA0, VIA1 and SER control I/O devices, not RAM or ROM. So those selects should appear in the I/O block, along with the expansion I/O selects. Assuming VIA0, VIA1 and SER are hardware that is a permanent part of the circuit (i.e., directly attached to the main board), they should be "hard wired" to the lowest of I/O block addresses, since they will always be there. If your I/O block starts at $00C000, for example, and each device is assigned a page of address space, which would be the case if decoding uses A15-A8, I'd make SER appear at $00C0xx, VIA0 at $00C1xx and VIA2 at $00C2xx. External I/O selects would start at $00C3xx, up to $00CFxx, which is the maximum supported range with eight bits of I/O decoding.

That said, you need to be realistic about just how much I/O you are going to need to make this work. Eight I/O devices is a lot of hardware for a typical 65xx system—I've not see a system with more than that.

Turning attention to the bank bits generation, you also need to be realistic about your requirements. Decoding all eight bits sounds good, until you consider the required logic resources and physical connections. What is the likelihood you will equip your machine with 16MB of RAM? Were I to hazard a guess, I'd say slim to none.

Merely providing A16-A23 won't do anything for you unless you have hardware populating the entire address range. Assuming the use of 512KB SRAMs to populate the full address space, that's 32 SRAMs required, which means 32 chip selects have to be generated. Then there is cost. At $5.89 each (current price at Digi-Key), those 32 SRAMs will come to nearly $190.00. I'm not trying to deflate your balloon, but these are things you have to consider before you build your 65C816-powered mainframe.

_________________
x86? We ain't got no x86. We don't NEED no stinking x86!

Top

banedon

Post subject: Re: Running buses off the main PCB, I/O on daughter board

Posted: Wed Aug 11, 2021 9:35 pm

Joined: Sun Sep 08, 2013 10:24 am
Posts: 740
Location: A missile silo somewhere under southern England

An update on this:

I did a test design for the memory card as I've not designed an edge connector based PCB before. Physically, it seems to be spot on. Virtually no give in the edge connector socket/slot (so the contacts line up nicely) and the pins buzz out fine.
I haven't got all of the components to fully populate the card at the moment, so have soldered on a DIP socket for the ROM and some of the bypass caps (1 for each power line and 1 for the ROM). The RAM is SMD (CY7C1049) and is currently on order with a few other bits.
I have a few ideas on improving things such as widening the edge connector contacts.

If anyone has any suggestions for improvments, feel free to say

Attachment:

A.gif [ 299.52 KiB | Viewed 169 times ]

Attachment:

B.gif [ 284.29 KiB | Viewed 169 times ]

Attachment:

C.gif [ 270.61 KiB | Viewed 169 times ]

Attachment:

D.gif [ 274.3 KiB | Viewed 169 times ]

Attachment:

E.gif [ 272.64 KiB | Viewed 169 times ]

Top

Page 3 of 3

[ 32 posts ]

Go to page Previous 1, 2, 3

Board index » 6502.org Users Forum » Hardware

All times are UTC

Who is online

Users browsing this forum: No registered users and 9 guests

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum