Hi Guys!

Thanks for welcoming me to your community, back over in my question thread. The responses have been truly amazing and I am quickly feeling that this is a great little community!

You'll find that my project is pretty bare bones at the moment as I am a complete newbie to the W65C02 CPU. But growing up as a kid with the Commodore 64 in the 80's has made me very fond of the 6502/10.

My lofty goals are to make a full computer with VGA output. Before you say "Oh god, here we go " don't stress, I'm in no rush and am in it for the long haul. And besides, I have already built the functional VGA board. I started this project in what people would consider to be reverse order.



Now we have that out of the way. I have started the CPU side of things by being very minimalistic, mainly because I am new to this side of things and will be very much experimenting with timings etc, until I get a firm understanding of what keeps the W65C02 happy. If it's happy, I'm happy!

This is the bare bones circuit that I have started with, that I will expand upon.



The reason for the inverter there, is related to the 'BE' usage question, where I wanted to be able to invert the clock and put the CPU in to high-Z on the lower cycle. As I have found, it's not as simple as just doing that (did have some success though yesterday) so the inverter can be ignored.

I created a stripboard, with heaps of header pins so I can connect other boards (like RAM etc.). I am pretty OCD with my stripboards. I tend to put the effort into going straight to stripboards as I am yet to find a breadboard that works reliably, they always seem to be a constant fight to get decent connections.



I have also made my own logic analyser, which I am monitoring the data and address bus with, and also acts as the clock to the 6502. Here's a pic of when I put it together after receiving the boards back from PCBWay after designing them. In the pic, I was just testing all of the I/O's to make sure it worked as planned, which it did!



The CPU gets it's ROM/RAM from another board I made which I call "FlashRAM 128". I needed a nice and easy way to be able to get programs to run on the 6502. It has a Raspberry Pi Pico, which pre-populates the RAM with whatever I want on it. It also holds the CPU in high-z, then resets it.

Here it is pre-loading the RAM on the aforementioned VGA card during early testing. The FlashRAM is the red board the VGA is two blue boards hooked together.



The 'FlashRAM' can either house a 128KB ram chip or can talk to external directly RAM.

So here it is in its present form, all interconnected. I am dumping the program directly on to the VGA RAM board (holding the rest of the VGA boards circuit in high-z, so the CPU has exclusive use right now) and it is all happy running a simple program at around 2 Hz.





I know I'm not going to win any speed records with the current setup, it's purely to gain confidence and understanding of how the 6502 ticks.

So there you go! A fairly long winded first post. But hopefully this will give a bit of an insight as to where I'm coming from. Not afraid to get my hands dirty and not afraid to put my hand up when I don't know something. Hehe!

All feedback and questions are welcome.


(Typo in the reset vector - should read $C0 not $DC0. I mustn't have hit save last night when I corrected that)

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Hi BDD, thanks for the tips.

I mentioned in the thread that the clock source is presently a Raspberry Pi Pico, which I am also using to monitor and report back what is on the data and address lines. I measured the rise and fall times and they are both around 4.5ns.

With the 74LS04, I also mentioned that it has been removed from the circuit entirely and can be ignored from the schematic.

I certainly wasn't aware of not requiring pull-ups on the address lines. I'll look at removing those. FWIW - My diagram says 2.0K on all of the resistors. But I opted with 3.3K in the end. I think it was Garth's primer that made me go for higher values in the end. I didn't want to inadvertently load things down too much.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Awesome! Many thanks for the clarification. Even makes the circuit much simpler as a result.

I've updated the core of the project, removing the unused IC and capacitor, also removed the bus pull-ups as per BDD's suggestion. Changed the values of the resistors to 3.3K to reflect what I have in the prototype board. I'll leave the data line pull-ups in the circuit diagram for now and look at the possibility of removing them as the project matures.

Is this because of the logic levels?

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Thanks for the detailed reply.

So going by the manual (and assuming 5v as he source), an acceptable logic high is 3.5v to 5.3v and low is -0.3v to 1.5v.

That gives a pretty nice leeway compared to TTL. I can certainly see why TTL is not a very good choice when interfacing it directly to the W65C02.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

It's funny that you mention that, because I been doing some tests of my own this evening (I'm very much a try things in practise kind of person) and found some interesting results.

I was looking at making a better clock circuit by feeding a ~25 MHz oscillator can in to a 74HC4040, so I can use that as a clock divider. Maybe even cascading two of them so I can keep halving the clock all the way down to around 1Hz at the extreme low end.

Running all of this initially from a bread board (which I'm not a huge fan of at the best of times) gave me this lovely wave form, at one of the 74HC4040's outputs.



Needless to say I was mortified by the result.


So I thought I'd do some experimenting. Starting by placing the components close together using standard hook up wires.

The result was much better.




Which then got me thinking. What if I take Garths advice and take the shortest path?




Even better! Now let's see what happens if we add icing to the cake by adding a 0.1uF capacitor (shortest path again) across the supply pins?




Even better again!

So it just goes to show you, placement is absolutely key! Not that I ever doubted you. But it's a very interesting exercise to see the different before your own eyes!

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Very true! Or I could even ditch the breadboard power rails and go direct. I might try that out in the morning, out of interest. All packed up for the night here (in Australia).

Abstract side question.

If a HC CMOS (assuming 5V power source) sees a logic low as 0V to 2.1V and a logic high as 2.4V to 5V, that would make the rise time here 0.32nS wouldn't it?

You'd calculate the time between the 'valid' states for the device type wouldn't you? Obviously taking consideration of the type of the next device in the chains capabilities.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?