Some very interesting points there too! Would it be better to run the CPU at a lower voltage, in the meantime (obviously at the cost of top end clock speed, which isn't a real concern to me at this point).

The RAM I am using is ISSI61C1024AL and it's guaranteed high is in fact 2.4v.

Although, measuring with the oscilloscope it is pumping out a solid 4.4v on the data and address lines (even with the pull down resisters in place). But, certainly something for me to keep in mind.

With where I am at right at the moment, I have a quick break down of what the CPU is doing.



Keep in mind I'm still a newbie to 6502 coding, but it appears to be storing (or trying to store) $C008 on the stack, probably so it knows where to jump back to? Is this right?

So would this indicate that I need to investigate the read/write timings?


[edit]

A bit of further investigation. This is where I'd love to have a four channel oscilloscope. LOL

It looks like I need to address those write times. Be back soon! Haha!

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

That is very awesome indeed!


Not sure on the rise time, I'll have to look deeper in to that.


Nice pick up! Although the source code is very much LDX#.



So, either I have a loose connection on the data lines somewhere, or the rise/fall times on the RAM are already coming in to play. Thinking about it, loose connection would be more likely wouldn't it? Running at 1Hz, is should be well and truly stable when PHI2 goes low (shouldn't it?).


[edit]
Yep! Some profuse wire jiggling bout it back to 'A2' at that location. Still going off in to 'no mans land' midway through the program, I'll double check the reset of the program matches up and then look at addressing this write signal.

Any particular reason you do a CLC?

Unlike ADC and SBC, CMP ignores the state of the carry flag.

Yep, because I am a newbie. Nothing more than that.


[edit]
Oh and after all that, I was using pull up resistors. Been a while since I looked at my circuit diagram. 3.3K pull ups.

Just a quick note: beware of updating posts by editing them. Anyone who saw them before your update will miss it. I recommend posting an update instead - multiple posts from the same person is no problem, if there's a reason for them.

On the topic of mega-threads, I'd distinguish between the one case, where it's a project log showing development progress, and the other case, where it's a series of interesting and difficult problems to be solved. In that second case, a thread for a problem, with a suitable subject line, is much much better for future reference. This site is such a good resource in part because it has so much history, and that's much more useful if it can be found.

As Garth notes, making links forwards and backwards to join related threads is good practice too. For example, a project thread would link forwards to a problem thread, and the problem thread would link back to the project thread.

Awesome! Thanks for the heads up.

So now that this is becoming more of a 'dev log' and observations, do you think I'd be better off starting a new thread in Hardware and call it "J64C's Homebrew" or something? Seems like a good idea to me.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Nope, nothing on the IRQ lines. They are tied high via 3.3K resistors.

I'm suspecting the CPU is just getting corrupted somewhere due to my timings (as I am only running on the high phase of PHI2). I'm simplifying the circuit again, as I type, to get it back to bare basics, making sure my read/write operations are performing correctly with a full clock. Once, I'm happy with that, I'll go back to getting it working on just the high phase.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thankfully, I'm a very meticulous person. I know, it's one thing saying it and another thing proving it, which hopefully over time you'll see, once you get to know me. I'm not a big fan of "it works but I don't know why".

I'm also the first to admit where I don't know something, which is the other half of the battle (and there is tons I don't know).

I think I will make a topic dedicated to the build. Kind of a 'dev log' where I can show progress, fails, and successes, as the project takes life. Even though the 'homebrew computer' side of it is just beginning, it is already a culmination of five separate projects that I have created over the past year to get where it is now. So hopefully someone might find it interesting.

Hello, J64C. Just a reminder that it really is better to attach images to your posts (rather than using a third-party image hosting site). Maybe if you get a minute you could accordingly update your posts in this thread, pls & thx.

Okay, you've clarified that there are 3.3k pullups in place. This will explain the nice, high levels on the data lines. But the RAM's address lines are inputs, so the levels you see there are pumped out by the CPU, not the RAM.

Looking forward to seeing a schematic, BTW!

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Done!

Just created a thread about my little 'homebrew' (or lack thereof ) over here - viewtopic.php?f=4&t=6688