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PostPosted: Sun Jul 11, 2021 11:40 am 
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Hi guys

I'm trying to design a very compact, basic board for prototpying I/O.
The project will consists of :

Mainboard
Power rail at 5V
Clock & reset circuits
65816 cpu - planned 8MHz speed, higher if I can wangle it
1 to 16MB SRAM
12KB ROM
Glue logic CPLD
Upper 8bit address Latch

I would like to have all of the I/O run from a daughter board, so plan to run A0-15, D0-15, IRQ device inputs, I/O, Selects, PHI2, RWB, RESB, etc. all off of the board. The connector would be a pin header-to-edge connector or just pin header.
Given that it's not recommended to run buses directly off the board, I was wondering if it would work if I used transcievers - at least for the buses? I'm thinking the show-stopper might be the timings, but if I keep PHI2 low enough it might be fine?

Transciever allocation and direction
Address bus - uni directional outbound, 2 x 8 bit [edit: I might just make this A0-7 as I can't think of why A8-15 would be needed]
Data bus - bidirectional, 1 x 8 bit
I/O selects for VIAs, Serial, etc. - uni directional outbound, 1 x 8 bit
IRQ for VIAs, Serial etc. - uni directional inbound, 1 x 8 bit

Transciever
I'm currently looking at the TI SN74AC245. It has a 1 to 9ns delay across it A to B, B to A, /OE would be tied low (active) so no delay there.
The edge rise time says 8ns per volt which means potentially uyp to 40ns transition time of logic level change? Or am I getting that wrong?
If anyone knows of a better device then please let me know.

Designing
I'm going to design the project, post the circuit design here (not dealt with 65816's before so want the bus decoding checked) and then will have a PCB made. I would do it via wirewrap/point to point or breadboard, but the sockets for ww are expensive and I hate doing the latter two due to the number of connections involved.

Does the above sound feasible? If so, are there any gotchas I should look out for?


Last edited by banedon on Sun Jul 11, 2021 3:53 pm, edited 2 times in total.

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PostPosted: Sun Jul 11, 2021 12:38 pm 
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banedon:

I had a quick look-see at the data sheet for the 'AC245 you referenced above. Something in your statement did not seem right:
banedon wrote:
The edge rise time says 8ns per volt which means potentially up to 40ns transition time of logic level change? Or am I getting that wrong?
The only dT/dV specification that I found in the data sheet on my quick read is the one referring to the input transition time. This means that for the part to operate correctly, circuits external to the part need to ensure that their outputs transition at rates exceeding 8ns/V. If signals with slower transition times are presented to the inputs of the 'AC245, the part may not operate correctly. For example, it may break into oscillation as the input signal slowly transitions through its input threshold voltage region.

The output transition rates of the part are not specifically identified. You should understand that the output transition times of this logic family are quite fast, and limited only by the load, primarily the load capacitance, that your design presents. In my experience, the output transition times for these advanced logic families would be difficult for you to measure with the typical test equipment we are able to afford as hobbyists.

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PostPosted: Sun Jul 11, 2021 1:14 pm 
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Hi Michael

Thanks for replying. I thought I might be misunderstanding it - many thanks for clearing that up :).


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PostPosted: Sun Jul 11, 2021 4:03 pm 
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The recommendation in the 6502 primer not to run the buses off the board has to do with AC performance, not drive capability. WDC's processors' pin drivers are more than ten times as strong as the data sheet lets on, as discussed in the middle of the page of the 6502 Primer's section 5. 74ACxx outputs' rise and fall times will be just as troublesome for putting out on a bus. That's not to say it can't be done; it's just that you'll have to really pay attention to line lengths and reflections and so on. It was a lot easier decades ago when parts didn't have the super-fast rise and fall times that cause the "splashing" when the math of transmission lines is not paid close attention to. Putting memory on small daughter boards on the main board will be far less troublesome than putting everything out on a backplane, as the connections will be shorter.

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PostPosted: Sun Jul 11, 2021 6:03 pm 
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Thanks for advising, Garth.
Part of my issue is PCB real estate and other is having the ability to just reconfigure I/O easily so i can have cards etc.
If I move the RAM and ROM to a daughter-board this will help with the former, but will not entirely work for the latter. I'll have a think on it, but I guess I'll most probably have to put the cards on the I/O pins of the VIAs.

Cheers again


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PostPosted: Sun Jul 11, 2021 6:44 pm 
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Hi Bandeon, I've actually done exactly this for my "GameTank" project. The latest boards are a stack of two, with the processor on the bottom and audio/visual signal generated on the top. I'm still wrapping my head around the transmission effects I've largely conquered by happy accidents, but I did have one practicality note come to mind:

Using pin headers will become quite frustrating with that many lines as they deform a tiny amount with each disconnect. Initially it was easy but over time I had to start using a screwdriver to work them apart for inspection.

I'm a fan of the card edge connectors since I'm nostalgic for game cartridges, though they can take up a lot of space and require significant force.

A connector I've gotten great use out of for daughterboards is the TX24/TX25 connector from JAE. It's available in through-hole, is decently easy to solder, and the simple snap-in connection has been quite reliable. They also make it easier than with card edge connections to put the boards parallel, or make any guarantees about physical alignment.


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PostPosted: Sun Jul 11, 2021 8:24 pm 
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Hi Agumander

Thanks for the heads up regarding the pin distortion and also the TX14/TX25 connectors. The ones I was looking at were these for edge connectors:
https://uk.farnell.com/amp-te-connectiv ... dp/2838988


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PostPosted: Sun Jul 11, 2021 8:55 pm 
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banedon wrote:
I'm trying to design a very compact, basic board for prototpying I/O...I would like to have all of the I/O run from a daughter board, so plan to run A0-15, D0-15, IRQ device inputs, I/O, Selects, PHI2, RWB, RESB, etc. all off of the board.

As Garth noted, running the buses off-board can give rise to some...ahem...interesting issues. Although the 65C816 develops adequate drive, transmission line effects will likely get into the picture. You can get some guidance by looking at how it is done in older PCs. The ISA bus was effectively an extension of the processor buses, but everything was buffered, including the clock, read/write signals, etc. In the days of 74LS logic, buffering served the twin purposes of generating adequate drive and minimizing signal skew that can raise havoc with timing.

Drive is less an issue these days, so that aspect of bus design isn't as important as it was in the past. However, buses of any significant length should be terminated to minimize reflections. Additionally, traces should be carefully routed to achieve short paths and to minimize Vcc sag and ground bounce—use of a four-layer PCB with power and ground layers can do a lot to help with the latter problems. The quality of construction becomes more important as you ramp up the clock.

Quote:
The connector would be a pin header-to-edge connector or just pin header.

I would use an edge connector, not pins. Pin connectors were popular years ago in minicomputers and some micros, but fell out of favor when it was discovered that edge connectors tend to insert less parasitic capacitance into the system. Also, they are easier to line up during card insertion.

Quote:
Given that it's not recommended to run buses directly off the board, I was wondering if it would work if I used transcievers - at least for the buses? I'm thinking the show-stopper might be the timings, but if I keep PHI2 low enough it might be fine?

With the 65C816, ideally a transceiver should be used to isolate the data bus from the MPU during Ø2 low—WDC shows that in the 816's data sheet on page 44 in the 2018 edition. I should mention that none of my POC units to date have used a data bus transceiver—POC V1.2 was stable at 20 MHz and POC V1.3 is stable at 16 MHz. That said, use of a bus transceiver slightly delays the transmission of data to/from the MPU so that it doesn't start until about 8ns maximum after the rise of Ø2. Similarly, the transceiver will hold the bus state about the same length of time after the fall of Ø2. This behavior may be beneficial in some cases.

Quote:
Transciever
I'm currently looking at the TI SN74AC245...

I'd recommend using the 74ACT245. This is a 74AC245 with TTL-compatible inputs. Not all available devices generate CMOS output levels. For example, a lot of SRAMs and EPROMs have TTL-level outputs.

Quote:
.../OE would be tied low (active) so no delay there.

/OE should be gated by Ø1, which is the inversion of the Ø2 clock. You especially do not want the transceiver driving the D0-D7 pins of the 65C816 during Ø2 low, as the result will be major data bus contention—the 816 will be emitting A16-A23 on D0-D7 during that time.

Keep in mind that it is the fall of the clock that matters in a 65xx system. Hence the delay from when the transceiver's /OE is asserted to when the transceiver actually "conducts" is not an issue as long as the transceiver is fast enough to meet the setup time of the slowest device on the bus.

Quote:
The edge rise time says 8ns per volt which means potentially up to 40ns transition time of logic level change? Or am I getting that wrong?

What that means is anything that drives the transceiver's inputs must exhibit no more than 8ns/volt rise and fall time. The 74AC245's outputs are very fast, on the order of 1 to 2 ns total rise/fall time.

Quote:
Designing
I'm going to design the project, post the circuit design here (not dealt with 65816's before so want the bus decoding checked) and then will have a PCB made. I would do it via wirewrap/point to point or breadboard, but the sockets for ww are expensive and I hate doing the latter two due to the number of connections involved.

The cost of having PCBs made has dramatically dropped to the point where I wouldn't consider point-to-point or wirewrap anymore. JLCPCB is a good choice for PCBs, as they produce a quality product at a reasonable price. I had JLCPCB make the boards for my POC V1.3 unit—I was quite satisfied with what I received.

Quote:
The ones I was looking at were these for edge connectors:
https://uk.farnell.com/amp-te-connectiv ... dp/2838988

That is a good choice—TE makes a quality product. I recommend you use something with more than 24 pins. Believe me when I say you will wish you had more pins when you get done with your design. :D At the least, you definitely should have multiple ground and power connections.

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PostPosted: Sun Jul 11, 2021 10:27 pm 
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BigDumbDinosaur wrote:
ideally a transceiver should be used to isolate the data bus from the MPU during Ø2 low
Yes, there are various benefits to isolating the data bus from the MPU. In your case, banedon, your intention is to attach a very large amount of RAM, which means a large amount of capacitance on the bus. It'll be better to let a transceiver -- not the CPU -- shoulder the burden of charging and discharging that load.

Also, remember that the MPU data bus is twice as "busy" as the demux'ed data bus downstream of a transceiver. That's because the MPU bus is driven to a different state on each phase. From the POV of your expansion bus, you'll greatly reduce challenges such as transmission-line effects if the expansion bus only carries the comparatively leisurely demux'ed data.

-- Jeff

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PostPosted: Mon Jul 12, 2021 9:39 pm 
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I'm working on a couple of 65c816 designs based of what you guys have said. This is the one which does as Garth suggestions and runs the memory off the board rather than the I/O. The other one I'll probably finish tomorrow which shows the I/O running of the board instead.
Please note this design is quite rough, but I think I've gotten it right for the most part, although I have a concern about the number of grounds and +5V lines in the RAM/ROM header (i.e. are there enough?). The PCB will be 4 layer: 1:signals, 2:gnd plane, 3:pwr plane, 4:signals.
Note that each VIA has two sets of pin headers: one for vertical and one for horzontal which can have a pin header-to-edge connector fitted.

[edit] I forgot to link the RWB_E on the RAM/ROM header - this will become RWB and the one next to it currently not used will become /RD.
I also have the issue, not previously considered ( :lol: ), that I need to qualify how the memory is mapped by the CPLD (ATF1504AS) as I now have a 24 bit address, with atleast the top 16 bits needing to be validated. What I might do is feed A15-A8 into the CPLD and have A23-A16 fed into another CPLD or GAL... Can anyone think of a better solution?


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PostPosted: Tue Jul 13, 2021 5:10 am 
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I printed your schematic and have a few comments:

  1. In my opinion, 74HCT logic is too slow for the bank latch (IC9). I would consider using 74AC or 74AHC (the T variant is unnecessary in this application—also note the output transition rate of 74AHC is slower than 74AC, which may help in keeping a lid on ringing). The reason is the latch has to close following the rise of Ø2 before the MPU stops emitting the bank bits. Failure to meet this requirement will result in the latch reading data instead of bank bits very slightly before closing, which is almost a guarantee that the A16-A23 address component will be corrupted. This is a narrow timing window.

    See my below comments about detecting bank $00 accesses and other such malarkey.

  2. The 74HCT245 transceiver is likely too slow as well. Although the time required for it to start "conducting" when Ø2 goes high is not critical if not going for maximum performance, the time it takes to stop "conducting" when Ø2 goes low may be excessive and lead to short-term data bus contention during part of the Ø2 low phase when the 816 starts emitting bank bits. The exact effect of such contention could range from nothing to gross instability or a crash. Again, I would consider 74AC or 74AHC to minimize prop time. 74AC has harder drive than 74AHC, so it may be more appropriate in your system, due to bus signals being taken off-board.

  3. The 'C' input on the 573 latch (referred to as OE by some manufacturers other than TI) must be grounded. Otherwise, the latch will continuously high-Z its outputs and you won't have any bank bits.

  4. BE, NMI and RDY cannot all share the same pullup resistor. While it is possible to share that resistor between BE and NMI, I don't recommend doing so, as it closes the door to using either of those inputs in the future. NMI is useful for breaking runaway loops in programs, but can't be used as you've got it.

    RDY is bi-directional in WDC MPUs—it is driven low by the MPU when a WAI instruction is executed and stays low until a hardware interrupt is detected. WAI could accidentally be executed due a program crash or a simple program logic error. As you have it wired, if RDY is driven low it will take BE and NMI with it. Driving BE low will cause the 816 to high-Z the buses and RWB, possibly resulting in a system crash—assuming the spurious NMI doesn't get it first.

  5. Resistor R14 should be present even though oscillator OSC2 has CMOS output. R14 will help in suppressing ringing on the X1 clock going to the 28L92. I recommend using a metal film resistor, not carbon film, and definitely not carbon comp. I also recommend inserting a 100 to 150 ohm resistor in series with the oscillator's output to the DUART as a further ringing suppression strategy. Both resistors should be as physically close to the oscillator's output pin as possible for maximum effectiveness.

  6. In the same vein as the above, I recommend inserting series resistance into Ø1 and Ø2—a non-bused SIP resistor pack is good for that purpose. I've used values ranging from 100 to 220 ohms—some experimentation while observing the clock signal on your 'scope may be necessary. The resistor pack should be as physically close to the Q and /Q outputs of the clock flop as possible.

  7. The D input of the clock flop doesn't seem to go anywhere. Usually it is tied to /Q.

  8. If the 1504 CPLD is being used as glue logic it needs to know when an address is $010000 or higher. Otherwise, ROM and I/O are going to mirror in every bank and you will not have contiguous extended RAM.

    If the 1504 were in charge of generating the bank bits instead of a separate latch it would be easy to add logic that prevents mirroring in higher banks. Doing that with discrete devices is awkward at best and as I've noted in my comments about POC V1.3, will introduce prop delay that will limit the maximum speed at which your unit can run.

    The solution is to ditch the 573 and have the CPLD generate A16-A23. The logic is not complicated. However, you will need 16 uncommitted pins on the CPLD, eight to connect to D0-D7 on the MPU side of the transceiver and eight to output A16-A23. You will also need to supply Ø1 to tell the CPLD latches when to open and capture the bank address, as well as Ø2 to qualify your /RD and /WD outputs from the CPLD. Ø1 should come in on GCLK2 and Ø2 should come in on GCLK1.

  9. What's the purpose of tying IRQ signals to the CPLD?

  10. The 1504 generates TTL-level outputs, not CMOS. I recommend that all pins designated as outputs be pulled up to Vcc through 2.2K resistors. This is a good application for a SIP or SOIC resistor pack to save space and cut down on lead induction. The latter takes about less space with its 50 mil pin spacing and may be easier to route on the PCB.

  11. I don't see a JTAG header. This is a worthwhile addition, since it saves you the trouble of having to remove the 1504 each time you decided to change the logic.

  12. RESB should be pulled up to Vcc with a 3.3K resistor—I don't see one in your circuit. The pullup in the DS1813 is weak and if relied upon, will make the reset circuit vulnerable to noise.

  13. While on the subject of RESB, it should be connected to the GCLR pin of the CPLD. Otherwise, there is no input to determine when the RES output is to be asserted. The required logic in the CPLD is RES = !GCLR.

I may have missed something, but the above should get you started. :D

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PostPosted: Tue Jul 13, 2021 2:44 pm 
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banedon wrote:
I have a concern about the number of grounds and +5V lines in the RAM/ROM header (i.e. are there enough?).
Two each of Gnd and +5V ought to be sufficient, IMO. More would be somewhat better, but then you'd need a larger header.

You may also wish to be mindful of where the Gnd and +5V pins appear, as this has a bearing on AC performance. Just a reminder that every signal (eg A12, D4 etc) also causes current to flow in the Gnd and +5 lines in order to complete the circuit, and inductance is minimized when the signal has a return path that's physically nearby. Gnd and +5V are equally able to act as the return path. Whichever is closest will be the one that'll carry most of the current. (It's high-frequency AC that's at issue, not DC.)

So, the optimal strategy is to intersperse the 4 return lines among the signal lines rather than putting them at the ends of the header. The diagram below shows the general idea.

This isn't a matter that will make or break your design, so if you prefer a simpler arrangement that's OK. On the other hand, if you're aiming for faster clock rates and maximum performance then interleaved return paths absolutely deserve consideration.

-- Jeff


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PostPosted: Tue Jul 13, 2021 3:02 pm 
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banedon wrote:
Hi guys

I'm trying to design a very compact, basic board for prototpying I/O.
The project will consists of :

Mainboard
Power rail at 5V
Clock & reset circuits
65816 cpu - planned 8MHz speed, higher if I can wangle it
1 to 16MB SRAM
12KB ROM
Glue logic CPLD
Upper 8bit address Latch


Hi,

Hope it works out well - always good to have more '816 systems out there!

Mine "only" has 512KB of RAM, although I ought to be able to take it to 1MB without much difficulty (well, piggy-back chip soldering which I did for the 2 x 32KB chips on my 65C02 board) but really not sure what I'd use it for...

Re. your 12KB ROM - I treated bank 0 in mine like a BBC Micro, so 32KB RAM, 16KB "language" ROM, then 16KB OS (minus IO at $FExx) although it's really all RAM but that was the general idea. I can load BBC Basic into the language area at $8000 and run that in emulation mode, or my BCPL OS which runs in native 16-bit mode.

I have all that on a single board with 2 GALs for the address bus latch and address decoding (and some other little bits)

Cheers,

-Gordon

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PostPosted: Tue Jul 13, 2021 6:26 pm 
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BigDumbDinosaur wrote:
I printed your schematic and have a few comments:

  1. In my opinion, 74HCT logic is too slow for the bank latch (IC9). I would consider using 74AC or 74AHC (the T variant is unnecessary in this application—also note the output transition rate of 74AHC is slower than 74AC, which may help in keeping a lid on ringing). The reason is the latch has to close following the rise of Ø2 before the MPU stops emitting the bank bits. Failure to meet this requirement will result in the latch reading data instead of bank bits very slightly before closing, which is almost a guarantee that the A16-A23 address component will be corrupted. This is a narrow timing window.

    See my below comments about detecting bank $00 accesses and other such malarkey.

  2. The 74HCT245 transceiver is likely too slow as well. Although the time required for it to start "conducting" when Ø2 goes high is not critical if not going for maximum performance, the time it takes to stop "conducting" when Ø2 goes low may be excessive and lead to short-term data bus contention during part of the Ø2 low phase when the 816 starts emitting bank bits. The exact effect of such contention could range from nothing to gross instability or a crash. Again, I would consider 74AC or 74AHC to minimize prop time. 74AC has harder drive than 74AHC, so it may be more appropriate in your system, due to bus signals being taken off-board.

  3. The 'C' input on the 573 latch (referred to as OE by some manufacturers other than TI) must be grounded. Otherwise, the latch will continuously high-Z its outputs and you won't have any bank bits.

  4. BE, NMI and RDY cannot all share the same pullup resistor. While it is possible to share that resistor between BE and NMI, I don't recommend doing so, as it closes the door to using either of those inputs in the future. NMI is useful for breaking runaway loops in programs, but can't be used as you've got it.

    RDY is bi-directional in WDC MPUs—it is driven low by the MPU when a WAI instruction is executed and stays low until a hardware interrupt is detected. WAI could accidentally be executed due a program crash or a simple program logic error. As you have it wired, if RDY is driven low it will take BE and NMI with it. Driving BE low will cause the 816 to high-Z the buses and RWB, possibly resulting in a system crash—assuming the spurious NMI doesn't get it first.

  5. Resistor R14 should be present even though oscillator OSC2 has CMOS output. R14 will help in suppressing ringing on the X1 clock going to the 28L92. I recommend using a metal film resistor, not carbon film, and definitely not carbon comp. I also recommend inserting a 100 to 150 ohm resistor in series with the oscillator's output to the DUART as a further ringing suppression strategy. Both resistors should be as physically close to the oscillator's output pin as possible for maximum effectiveness.

  6. In the same vein as the above, I recommend inserting series resistance into Ø1 and Ø2—a non-bused SIP resistor pack is good for that purpose. I've used values ranging from 100 to 220 ohms—some experimentation while observing the clock signal on your 'scope may be necessary. The resistor pack should be as physically close to the Q and /Q outputs of the clock flop as possible.

  7. The D input of the clock flop doesn't seem to go anywhere. Usually it is tied to /Q.

  8. If the 1504 CPLD is being used as glue logic it needs to know when an address is $010000 or higher. Otherwise, ROM and I/O are going to mirror in every bank and you will not have contiguous extended RAM.

    If the 1504 were in charge of generating the bank bits instead of a separate latch it would be easy to add logic that prevents mirroring in higher banks. Doing that with discrete devices is awkward at best and as I've noted in my comments about POC V1.3, will introduce prop delay that will limit the maximum speed at which your unit can run.

    The solution is to ditch the 573 and have the CPLD generate A16-A23. The logic is not complicated. However, you will need 16 uncommitted pins on the CPLD, eight to connect to D0-D7 on the MPU side of the transceiver and eight to output A16-A23. You will also need to supply Ø1 to tell the CPLD latches when to open and capture the bank address, as well as Ø2 to qualify your /RD and /WD outputs from the CPLD. Ø1 should come in on GCLK2 and Ø2 should come in on GCLK1.

  9. What's the purpose of tying IRQ signals to the CPLD?

  10. The 1504 generates TTL-level outputs, not CMOS. I recommend that all pins designated as outputs be pulled up to Vcc through 2.2K resistors. This is a good application for a SIP or SOIC resistor pack to save space and cut down on lead induction. The latter takes about less space with its 50 mil pin spacing and may be easier to route on the PCB.

  11. I don't see a JTAG header. This is a worthwhile addition, since it saves you the trouble of having to remove the 1504 each time you decided to change the logic.

  12. RESB should be pulled up to Vcc with a 3.3K resistor—I don't see one in your circuit. The pullup in the DS1813 is weak and if relied upon, will make the reset circuit vulnerable to noise.

  13. While on the subject of RESB, it should be connected to the GCLR pin of the CPLD. Otherwise, there is no input to determine when the RES output is to be asserted. The required logic in the CPLD is RES = !GCLR.

I may have missed something, but the above should get you started. :D


Thanks for looking at the circuit :). I've gone through your points below with one or two questions:

1 & 2. Thanks for clarifying this. I've bnecome warey of using AC(T) due to warnings baout the high-low and low-high transitions speed causing ringing so have gotten into the habit of using HC(T)> i've modified the circuit.
3. Yep I forgot to reconnect that one :). Have fixed that.
4. The symbol is a bit misleading (I need to redefine it). It's actually a bus resistor with each connection having it's own 3k3 resistor. If I have room I'll introduce 2 pin headers for RDY, NMY, BE which would allow room for them to be used as you suggest.
5. I've changed the note to reflect R14 is not optional/should be metal film if possible.
6. I'll add a SIP in as you recommend. Can you advise why this is needed?
7. The D input connects to both the /PHI2 line which is in turn connected to /Q of the same flip flop? This is for IC4A.
8. I hadn't added the memory decoding in yet as I was still considering my options on how to deal with the decoding. Would the CPLD be fast enough considering your comments about the need for speed that you emntion in 1) ?
9. The CPLD deals with IRQ arbitration, but as I may need to free up pins for 8) I could move that to an AND gate IC (74HC21D). I'll also add a pull up for the Opendrain line which I forgt to add.
10. I'll add the recommended 2k2 SIP
11. JP3 is a stand in for a JTAG header, although not connected/realised yet. I will be adding one in properly.
12. I'll add a 3k3 to both RESB and the D1812


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PostPosted: Tue Jul 13, 2021 6:38 pm 
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Dr Jefyll wrote:
banedon wrote:
I have a concern about the number of grounds and +5V lines in the RAM/ROM header (i.e. are there enough?).
Two each of Gnd and +5V ought to be sufficient, IMO. More would be somewhat better, but then you'd need a larger header.

You may also wish to be mindful of where the Gnd and +5V pins appear, as this has a bearing on AC performance. Just a reminder that every signal (eg A12, D4 etc) also causes current to flow in the Gnd and +5 lines in order to complete the circuit, and inductance is minimized when the signal has a return path that's physically nearby. Gnd and +5V are equally able to act as the return path. Whichever is closest will be the one that'll carry most of the current. (It's high-frequency AC that's at issue, not DC.)

So, the optimal strategy is to intersperse the 4 return lines among the signal lines rather than putting them at the ends of the header. The diagram below shows the general idea.

This isn't a matter that will make or break your design, so if you prefer a simpler arrangement that's OK. On the other hand, if you're aiming for faster clock rates and maximum performance then interleaved return paths absolutely deserve consideration.

-- Jeff

Hi Jeff

Thanks for the advice on this. I went for the current arrangement mostly to keep the number of pins down and also allow for me being a twit and plugging the card in the wrong way around - bus contention would occur, but nothing gets a dose of unrestricted +5V, etc. :D. On that note, I've been thinking about putting a detection circuit on the memory card which lights a red LED (green if the correct way) if you plug it in the wrong way or something similar. Or go down the keyed edge connector route.
Back to the power and gns: What I might do is still expand the header and add extra +5v and gnds while trying to still keep the above "you plugged it in wrong" system. Worst case, as you say, it can stay as-is.


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