I've just tried a little circuit on my Replica 1 using a 74LS377 and some LEDs to test something else I want to build. I tied the 377 enable to /A000 from the Replica 1 expansion - this signal goes low when I write to any Axxx address. Then I simply connect the data bus from the 6502 to the inputs of the 377, and the outputs to some LEDs. My question is what is the easiest way to do the rising edge trigger to latch the data to the LEDs? After studying some timing diagrams I thought using phi1 would be ok - when writing to A000 it seemed to go high only when the /A000 signal was low and the data safely on the databus, but although the data settles properly I am noticing an initial flash. For the LEDs this is not a big deal, but for my real circuit this will be a problem. What I would like to avoid is having to gate phi2 or phi1 with r/w for example, since that would mean adding an additional chip, but of course if I have to then I have to. I am using a R65C02P.

Ken

viewtopic.php?t=1399

The '574 is good for an 8 bit output port. Also, check out some of Garth Wilsons address decoding for phase 2 incorporation into the address decoding on the 6502 home page. It helped me out.

- EyE

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65Org16:https://github.com/ElEctric-EyE/verilog-6502