No schematic is absolutely essential to me as well, especially for larger FPGA designs. Drawing a schematic of a couple of hundred IO lines? How is that useful? That is why I use gEDA PCB - an otherwise primitive and decrepit piece of software. However it shines when used with my workflow, and I am willing to put up with otherwise untenable defects and gaps, and a ridiculous learning curve (which I have to face over and over as I tend to take multi-year breaks between hardware projects)
gEDA allows me to just plop down footprints and draw traces. But more importantly, I can use
hand-built partial netlist files to create airwires (AKA ratsnest). Other packages start with a pileup of airwires so dense that it is impossible to make any sense of them. With gEDA, I create a few separate netlist files (text files with one line per net, a readable listing of connections) which are great documentation, for debugging and for posterity.
I generally make a power netlist, an address bus netlist, a databus netlist, clock netlist, and a control signals netlist. I load a single netlist into airwires, and route it, moving onto the next one. I can also assign a distinct trace color for each group of signals - or keep them all the same color. When done, I can light up individual nets/traces to verify them against datasheets or see shorts.
I can make footprints that specify functional names of pins, such as IRQ or D7, then make a netlist that reads like English:
Code:
DataBus0 CPU-D0 RAM-D0 ROM-D0
DataBus1 CPU-D1 RAM-D1 ROM-D1
etc. Or use a pin-numbered footprint when that makes more sense. Footprints are just text files.
I am not aware of any other PCB layout package that allows me such flexibility where it counts.
Oh, and it is opensource and it writes Gerbers.