Has anyone been able to measure this for an NMOS 6502? I'm wondering if it could save battery on my 6507 project by bringing RDY low with a 6532 then back high again after the timer expires.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Right, although it's not primarily a matter of the minimum clock speed. What's even more pertinent is the fact that NMOS logic isn't complementary. That is, the upper device on each "totem pole" is a pullup that never stops pulling up, which means it wastes power anytime the output needs to be held low. (By contrast, the upper device in a CMOS totem pole is a PFET that switches off when no pulling up is required.)

For the 6507 project, it might be feasible to actually power down then restart the CPU. Off hand, I don't think it would be too hard to do that without powering down the 6532. Hmm.. just need to remember that the latter will still need a clock signal in order for its timer to generate the wakeup interrupt. And you'd need to prevent spurious 6532 accesses except when everything is stable. Hmmm...

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

May I ask how much current the 6507 is using? At what clock frequency?

It's an interesting question. I expect it's not going to help much, certainly for NMOS and probably also for CMOS - this is a case where slowing or stopping the clock is worth something, but worth much much more in the land of CMOS.

It's not too difficult, I would think, to rig up a NOP tester in a breadboard and find out.

I think Jeff is on the right track... RTCs can run unattended and issue an alarm call to wake up the system. Getting a VIA to do the same is an interesting challenge.