BigDumbDinosaur wrote:
I doubt that driving RDY low on an NMOS part affects current consumption to any significant extent.
Right, although it's not primarily a matter of the minimum clock speed. What's even more pertinent is the fact that NMOS logic isn't complementary. That is, the upper device on each "totem pole" is a pullup that never stops pulling up, which means it wastes power anytime the output needs to be held low. (By contrast, the upper device in a CMOS totem pole is a PFET that switches off when no pulling up is required.)
For the 6507 project, it might be feasible to actually
power down then restart the CPU. Off hand, I don't think it would be
too hard to do that without powering down the 6532. Hmm.. just need to remember that the latter will still need a clock signal in order for its timer to generate the wakeup interrupt. And you'd need to prevent spurious 6532 accesses except when everything is stable. Hmmm...
-- Jeff
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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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