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PostPosted: Tue Jun 29, 2021 1:06 am 
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Has anyone been able to measure this for an NMOS 6502? I'm wondering if it could save battery on my 6507 project by bringing RDY low with a 6532 then back high again after the timer expires.


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PostPosted: Tue Jun 29, 2021 1:35 am 
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Druzyek wrote:
Has anyone been able to measure this for an NMOS 6502? I'm wondering if it could save battery on my 6507 project by bringing RDY low with a 6532 then back high again after the timer expires.

I doubt that driving RDY low on an NMOS part affects current consumption to any significant extent. It's not a static design, so register refresh must constantly occur, which means a minimum clock speed must be maintained at all times. On the other hand, the WDC 65C02's consumption goes down into the micro-ampere range when RDY is low, and is able to maintain state with the clock stopped in either phase. In fact, that's what driving RDY low does in the W65C02S: it stops the internal clock until a hardware interrupt is detected. The WAI instruction does the same thing and actually causes the MPU to drive RDY low while WAIting.

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PostPosted: Tue Jun 29, 2021 3:18 am 
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BigDumbDinosaur wrote:
I doubt that driving RDY low on an NMOS part affects current consumption to any significant extent.
Right, although it's not primarily a matter of the minimum clock speed. What's even more pertinent is the fact that NMOS logic isn't complementary. That is, the upper device on each "totem pole" is a pullup that never stops pulling up, which means it wastes power anytime the output needs to be held low. (By contrast, the upper device in a CMOS totem pole is a PFET that switches off when no pulling up is required.)

For the 6507 project, it might be feasible to actually power down then restart the CPU. Off hand, I don't think it would be too hard to do that without powering down the 6532. Hmm.. just need to remember that the latter will still need a clock signal in order for its timer to generate the wakeup interrupt. And you'd need to prevent spurious 6532 accesses except when everything is stable. Hmmm...

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Last edited by Dr Jefyll on Tue Jun 29, 2021 3:20 am, edited 1 time in total.

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PostPosted: Tue Jun 29, 2021 3:19 am 
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I just checked the Wikipedia article about NMOS to make sure of how I thought NMOS worked. Here's a quote from there: "The major drawback with NMOS (and most other logic families) is that a DC current must flow through a logic gate even when the output is in a steady state (low in the case of NMOS). This means static power dissipation, i.e. power drain even when the circuit is not switching."

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PostPosted: Tue Jun 29, 2021 8:26 am 
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May I ask how much current the 6507 is using? At what clock frequency?


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PostPosted: Tue Jun 29, 2021 8:30 am 
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It's an interesting question. I expect it's not going to help much, certainly for NMOS and probably also for CMOS - this is a case where slowing or stopping the clock is worth something, but worth much much more in the land of CMOS.

It's not too difficult, I would think, to rig up a NOP tester in a breadboard and find out.

I think Jeff is on the right track... RTCs can run unattended and issue an alarm call to wake up the system. Getting a VIA to do the same is an interesting challenge.


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