New life for an old J.P. Designs Parallel 65 SBC

[auldgeek]

Hello all ... back in 1989 I bought a J.P. Designs Parallel 65 SBC (*) for a model railway project. I still have the receipt, purchase price back then was £127.02! The project never went anywhere but I still have the SBC. The board has R6502A, 6264 8kx8 static RAM, 2764 8kx8 EPROM, R6551 ACIA, 4xR6522 VIA, and the following for glue logic: 74HC74, 74HC04, and 74LS138. Finally a 1488 and 1489 provide RS-232. The 138 decodes A13/A14/A15 to give 8 8k blocks, phi1 (yes phi1) being used as input to the 138 to qualify the /CE outputs. On the 6264 and 2764 /OE and /CE are connected together. The 6502 runs at 1Mhz.

Finding a bit of free time recently whilst other projects are on hold I decided to get the SBC out for a bit of fun. I removed the 1488 and 1489, fitted a couple of jumpers, connected a 5V RS232 to USB adapter, and applied power. It worked

Now thinking I'd like to get back into playing with the 6502 family - I had an Acorn Atom back in the late 70s and a loaner BBC micro in the early 80s. I'm contemplating upgrading to a WDC65c816, 32kx8 CMOS static RAM, and using a 8kx8 NVRAM (STMicroelectronics M48Z08-100PC1?) in place of the EPROM. Glue logic would be updated to decode 32k+(8*4k) and would use phi2 to qualify R/W to generate /OE and /WE. I'd also like to use the existing PCB as much as possible cutting a few tracks and rewiring where necessary. For the 65816 and new glue logic I'm thinking of a small point to point wired daughterboard connected to the 40 pin header conveniently provided on the original board which breaks out the original 6502.

This raises a couple of questions:
1. should it be ok to mix the modern CMOS chips with the older NMOS chips - I'd rather not replace the VIAs and ACIA if not necessary, in fact I'd rather retain the original ACIA in order to avoid the well documented transmit bug in the 65c51.
2. with reworked address decoding and glue logic nothing would require the old 6502 phi0 or phi1 so I assume I can just ignore those, simply rerouting the external clock that would have gone to phi0 on the 6502 to phi2 on the 65816.

I've noted the various posts and resources on 6502.org re replacing a 65(c)02 with an 65816 so am aware of the pins that have been repurposed and how they should be connected.

Anything strikingly wrong with the above approach? What have I missed?

This is my first post having lurked around for some time. Hoping to tap into the wealth of knowledge here in the forum.

(*) searching 6502.org and more widely has drawn a blank on J.P. Designs boards. Anyone else out there have one or remember them?

[BigDumbDinosaur]

auldgeek wrote:

Hello all ... back in 1989 I bought a J.P. Designs Parallel 65 SBC (*) for a model railway project...

First off, welcome!

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1. should it be ok to mix the modern CMOS chips with the older NMOS chips - I'd rather not replace the VIAs and ACIA if not necessary, in fact I'd rather retain the original ACIA in order to avoid the well documented transmit bug in the 65c51.

The NMOS inputs won't have any problem with the CMOS outputs. However, driving CMOS inputs with NMOS outputs can be dodgy, as an NMOS output's logic 1 is a lower voltage than that of a CMOS device. We know from testing, for example, that an input to the 65C816 when running on 5 volts needs to be 2.7 volts minimum for the 816 to recognize the input as a valid logic 1 (as an aside, this is substantially below what the data sheet says is a valid logic 1). The salvation is that if very lightly loaded, an NMOS output might rise into the low 3 volt range—the theoretical maximum is 3.4 volts, which is enough for the 65C816 to recognize it as a logic 1.

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2. with reworked address decoding and glue logic nothing would require the old 6502 phi0 or phi1 so I assume I can just ignore those, simply rerouting the external clock that would have gone to phi0 on the 6502 to phi2 on the 65816.

That's correct. My only caution is that you examine the Ø2 clock on a 'scope to verify that it swings rail-to-rail and that the rise/fall times are very short, ideally under 5ns.

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(*) searching 6502.org and more widely has drawn a blank on J.P. Designs boards. Anyone else out there have one or remember them?

I've never heard of them. Was this a UK product? By chance, do you have a schematic for it?

[BigEd]

Indeed welcome!

I see just a couple of matches for JP Designs in 1980's magazine scans - with an address in Oyster Row, Cambridge, which is very much a residential address, so a very small business one would think. (That'll be the Cambridge in Cambridgeshire of course.)

For example, in the May 1984 issue of Elektor, Control 65, a 6502 based microcontroller board:

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Applications within industry are countless and also extend into educational and experimental spheres, thus providing the ideal opportunity to gain familiarity with the 6502 microprocessor.

Also, in April 1986 Elektor, the Gimini 2 handheld controller, 6502 based with RTC and 16 character LCD display.

By 1989 JP Designs has moved to nearby Ely and is selling an EPROM eraser.

We can pick them up at that new address... in April 89 selling the Control 80, a Z80 controller board.

And in Feb 1993 we see them as JP Distribution, selling the Parallel 6502 ("64 I/O lines, 8 RAM, Monitor EPROM. From $180"):

By October 1993 they are selling build-your-own PC-compatible components.

[barrym95838]

Ed, your search skills never cease to impress me!

Oh, and welcome to the forum, auldgeek.

[BigEd]

Cheers Mike!

auldgeek wrote:

Hello all ... back in 1989 I bought a J.P. Designs Parallel 65 SBC (*) for a model railway project. I still have the receipt, purchase price back then was £127.02! The project never went anywhere but I still have the SBC. The board has R6502A, 6264 8kx8 static RAM, 2764 8kx8 EPROM, R6551 ACIA, 4xR6522 VIA, and ...
... I decided to get the SBC out for a bit of fun...
... It worked :D

That's great!

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This raises a couple of questions...

I'm certainly interested as to how you get on (sorry I have no specific advice)

[auldgeek]

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First off, welcome!

and

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Indeed welcome!

thanks, great to be joining the forum, and I really appreciate the quick responses

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The NMOS inputs won't have any problem with the CMOS outputs. However, driving CMOS inputs with NMOS outputs can be dodgy, as an NMOS output's logic 1 is a lower voltage than that of a CMOS device. We know from testing, for example, that an input to the 65C816 when running on 5 volts needs to be 2.7 volts minimum for the 816 to recognize the input as a valid logic 1 (as an aside, this is substantially below what the data sheet says is a valid logic 1). The salvation is that if very lightly loaded, an NMOS output might rise into the low 3 volt range—the theoretical maximum is 3.4 volts, which is enough for the 65C816 to recognize it as a logic 1.

I've added my emphasis ... looks like mixing CMOS and NMOS is asking for trouble.

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My only caution is that you examine the Ø2 clock on a 'scope to verify that it swings rail-to-rail and that the rise/fall times are very short, ideally under 5ns.

See below for what the clock output from the 74HC74 looks like - rail to rail pretty much with some ringing, but not quite <5ns rise and fall. Adds more to the potential troubles!

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Was this a UK product?

BigEd has done an amazing sleuthing job in giving an insight to the history of this small UK company. Thanks BigEd

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By 1989 JP Designs has moved to nearby Ely ...

Image below of user manual cover confirms this.

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By chance, do you have a schematic for it?

The user manual includes a 'circuit diagram' as shown below. Not quite sufficient in itself, for example not showing that the output enables and chip enables are tied together on the ROM and RAM.

BigEd - your research brought back many happy memories of visiting the newsagent's as a teenager. No top shelf for me (ahem!). I started with Everyday Electronics, then progressed to Practical Wireless occasionally, Practical Electronics, Elektor, and ETI. Almost certainly I ordered my Parallel 65 from one of those!

But enough reminiscing ... what am I going to do? My thinking is now more like:
1. Still try to use the existing PCB - it is only double sided so should be easy enough to cut tracks and rewire as needed
2. Switch to use of CMOS throughout, i.e. 65c816, VRAM (in place of EPROM), RAM, 65c22 (noting the difference in IRQ treatments for N and S variants), 65c51 (using 65c22 timer to work around transmit bug), and of course CMOS glue

I shall explore some different memory maps and address decoding and see if I can figure a solution that gives me more RAM, maintains the 4 VIAs and ACIA, but manages to fit the glue logic into 2 14pin and 1 16pin devices to fit in the existing sockets. If I can't do that then I'll revert to the daughterboard on the 40 pin header idea. It would be nice though to keep everything on the original board

Again, many thanks for the warm welcome, your insightful replies, a reminder of teenage excitement, and, along with the rest of the forum, providing much for me to ponder upon. No doubt I'll be back soon as I get into the detail and see how much life I can inject into this old board.

[floobydust]

In addition to another Welcome... that appears to be a pretty nice board... hacking it up (slicing land patterns, etc.) seems like a pity. Another member recently hacked up a Commodore 1581 drive to get a CPU and couple other parts. Those drives fetch some pretty good money, but it was pretty hacked up. Then again, no idea what the board you have might be worth... probably not much, but still.

So, perhaps a different approach. I would look at making a daughter board that can plug into some of the existing sockets for the logic chips and RAM/ROM chips. That single board could then hold a 32KB RAM, 32KB EEPROM and either some logic chips for glue, or just replace all of them with a single ATF22V10. The one chip can yield qualified read and write signals, RAM and ROM chip enables and up to 5- 32-byte wide I/O selects. Also, just add a single half-size can oscillator and a DS1813 reset chip and momentary switch and you will have a nice little hardware board for doing some fun stuff.

As for CMOS/NMOS... you can likely still find an older Rockwell R65C02 as well as the CMOS versions of the 6551 and 6522. I bought quantities of all of these some years ago from UTsource. At a minimum I would suggest starting with a Rockwell R65C02 to replace the NMOS 6502... I've done this upgrade in multiple Vic-20 machines and several 1541 disk drives... no issue at all. Having access to the additional instructions and addressing modes can be quite useful.

[BigEd]

I tend to agree - it would be a bit of a shame to hack the board about. If you can use existing connectors and sockets to make the enhancements you're thinking of, that would be nice. Although of course it's your board.

As for mixing TTL and CMOS, it can be done, but you might need to look more carefully into what you're doing, and you might find yourself doing some detailed diagnosis and debugging. Keeping things simple has its merits. (Bear in mind that there are many families of 74 series, with different drive strengths and different logic levels.)

I quite like the simple world of binary signals which change once and decisively in each clock cycle, but in the real world there's a bit more going on.

Of course, you might enjoy diagnosis and debugging!

(Ah yes, Practical Electronics was a very important part of my self-education in electronics!)

[auldgeek]

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hacking it up (slicing land patterns, etc.) seems like a pity

and

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it would be a bit of a shame to hack the board about

Very fair comments and maybe I'm being a bit hasty in seeking to put the board under the knife As mentioned earlier the board does have a 40 pin header that breaks out the processor socket, so it would be very easy to use this for a daughter board. The 138 could be removed making the VIA, ACIA, and memory /CEs available via a 16 pin DIL header that could be connected to the daughterboard. This would allow a different memory map / decoding scheme to be used with the existing board. I'd still probably want to make a couple of small mods to the board, e.g. separating out /OE from /CE on the memory sockets, and adding A13 and A14 to the RAM socket to allow use of a 32k device.

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... or just replace all of them with a single ATF22V10

Till now I've been thinking 74 series CMOS chips for glue, but only out of sheer ignorance of what's needed to use PLDs. More to explore! Much to ponder, and still a long way from analysis paralysis

[GARTHWILSON]

Take a look at Daryl's glue-logic 22V10 which, AFAIK, he still supplies, pre-programmed: https://sbc.rictor.org/decoder.html

[BigDumbDinosaur]

auldgeek wrote:

1. Still try to use the existing PCB - it is only double sided so should be easy enough to cut tracks and rewire as needed

Like the others, I'd be reluctant to butcher the board. As with the early KIMs, what you have may have collectors value. It would be unfortunate to destroy that value.

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2. Switch to use of CMOS throughout, i.e. 65c816, VRAM (in place of EPROM), RAM, 65c22 (noting the difference in IRQ treatments for N and S variants), 65c51 (using 65c22 timer to work around transmit bug), and of course CMOS glue

Replacing the 6502 with a 65C02 would make more sense in this context. The 65C816 emits the bank bits on the data bus during Ø2 low, which might lead to bus contention and instability in this unit. A bus transceiver slaved to Ø2 and RWB would eliminate contention, but again, would require some butchering. The 65C02 wouldn't give rise to this problem.

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I shall explore some different memory maps and address decoding and see if I can figure a solution that gives me more RAM, maintains the 4 VIAs and ACIA, but manages to fit the glue logic into 2 14pin and 1 16pin devices to fit in the existing sockets. If I can't do that then I'll revert to the daughterboard on the 40 pin header idea. It would be nice though to keep everything on the original board

What you are suggesting would be bringing you perilously close to scratch-building a computer. As I said above, I'd be reluctant to butcher this unit and would instead consider building something else if you wish to do what you are describing.

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...looks like mixing CMOS and NMOS is asking for trouble.

It can be. As Ed noted, you need to carefully study what is driving what to identify likely trouble spots. Reiterating, a CMOS output into an NMOS input is no problem. The reverse may be a problem...it depends on circuit loading and to a lesser extent, the maximum rise and fall times that the device being driven can tolerate.

Case in point: my POC units all use an SRAM with TTL-compatible inputs and outputs, this in a circuit that is 100 percent CMOS. It works because the 65C816's inputs are more "sensitive" than the data sheet indicates. In general, it seems modern devices with TTL-compatible outputs like the SRAM (and the EPROM) I use have significantly more fan-out capability than their predecessors of the 1980s. Considering that a CMOS input draws virtually no current once the circuit's state has settled, that helps to minimize loading. The odds are pretty good that a modern TTL output will adequately drive a CMOS input.

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See below for what the clock output from the 74HC74 looks like - rail to rail pretty much with some ringing, but not quite <5ns rise and fall. Adds more to the potential troubles!

Yes, I'd expect rail-to-rail with a 74HC device—didn't know that was the clock source. The rise/fall time is not a problem with a Rockwell 65C02, but might be with a WDC 65C02. You'd have to test to be sure. Worse comes to worse, you can replace the 74HC74 with a 74AC74, which will easily meet the 5ns requirement, albeit with a little more ringing.

Speaking of ringing, what I see on your 'scope capture doesn't appear to be anything about which to worry.

Something to consider as you ponder your options with this unit is the construction of the unit will likely dictate the maximum speed at which you can reliably run, no matter what parts have been installed. As has been noted around here many times over the years, you can get away with murder at 1 MHz. Once you start ramping up the clock things can go haywire due to parasitic capacitance, series inductance, insufficient bypassing, minor timing "gotchas," etc.

[floobydust]

Here's a pic that shows the glue logic from my C02 Pocket SBC. You can see what actual signals from the CPU are required and what you get for outputs. Between the RAM/ROM sockets, the 74LS138 socket and the 555 timer socket, you can likely get all of those signals and then drive the rest of the PCB from there.

A shown, you'll need the clock signal that drives the CPU, the top 11 address lines and the R/W line. The /MRD and /MWR are the memory read and write lines, RAM and ROM obvious... and then of course the 5- I/O selects. What's shown as the signal name are the actual hex starting addresses for each.

Also note that using an EEPROM might be advantageous... as you can use some code to program it insitu... of course you need to be careful to ensure you don't load bad code... otherwise it may not boot up

[BigDumbDinosaur]

floobydust wrote:

Here's a pic that shows the glue logic from my C02 Pocket SBC...the top 11 address lines and the R/W line.

That is awfully dense address decoding, and is eating up scarce GAL inputs. I would not have made the I/O "windows" so small, nor would I have placed them smack in the middle of the $Fxxx block. I prefer to maintain contiguous ROM in the high pages to maximize code space.

[floobydust]

BigDumbDinosaur wrote:

floobydust wrote:

Here's a pic that shows the glue logic from my C02 Pocket SBC...the top 11 address lines and the R/W line.

That is awfully dense address decoding, and is eating up scarce GAL inputs. I would not have made the I/O "windows" so small, nor would I have placed them smack in the middle of the $Fxxx block. I prefer to maintain contiguous ROM in the high pages to maximize code space.

Well, there is a method to the madness... I prefer the I/O block (or even a page) at $FE00. My logic is simple: Pages 0 and 1 are special with the 6502... Page Zero and the Stack. The top page ($FF) contains the hardware vectors for Reset, NMI and IRQ/BRK. Logically, this is always going to ROM (or RAM loaded with some code before the CPU comes out of Reset). In between these four pages is all memory... so you can obtain a contiguous 63KB of memory, which could be all RAM as well.

As for the smaller I/O blocks (windows), I've found that a 32-byte wide I/O select can do a fair amount. The 6522 is only 16-bytes wide, so two can be selected with a single I/O select. Also, my recent RTC/CF Card adapter uses a single I/O select and can access the full register set for the DS1511, the full set of registers and chip selects for the Compact Flash card and the upper 8-bit latch for 16-bit data transfers.

Granted, my memory map may not satisfy everyone.... but it works perfect for the confines of the C02 Pocket and it's expansion connector as show below:

[1024MAK]

Things that I would be thinking about if I owned this J.P. Designs Parallel 65 SBC:

How much it is worth depends on how much people are prepared to pay for it. Not always, but sometimes obscure but rare items can suddenly gain value at some magic point in the future.

I don’t think I would want to cut tracks if it were mine. If it was a minor alteration to keep it working due to the unavailability of a part, that’s one thing. Or if it is a common mass produced item (e.g. one of the very common eight bit home computers), then I would not have a problem with hacking one of these (there already being countless examples that have been ‘preserved’). But with the modifications that you are thinking about, especially if you want to increase the clock speed, or use modern CMOS parts, it may well be better to design a new PCB.

So that gets back to the old, but often repeated question: what is your objective?
Is the fun trying to improve an old, existing board?
Write code for or play with a 65C816?
Just get back into 6502 coding?
Get a 6502 board with various I/O to play with interfacing to various external devices?
Something else / none of the above…

Although it is nice to maximise the amount of memory (be it RAM or some type of ROM), 8k bytes is plenty if you will just be playing and having fun with assembly language coding. Or if playing with interfacing to various external devices.

If you do decide to produce a PCB design of daughter board, do compare how this may go compared to designing your own SBC PCB.

Mark