Jmstein7 wrote:
I started these little experiments because I just could not get an external bus to work on our SoC - even when I added the address lines back in to the external outputs. So, I thought it might be the core.
There are a couple of changes you could experiment with.
1. Add a register to capture data on the falling edge of Phi2:
Code:
reg [7:0] bus_data;
-- capture the bus data on the falling edge of Phi2
always @(negedge Phi2) begin
bus_data <= data_io;
end
-- use the registered bersion of bus data
assign cpu_din = ram_e ? ram_dout :
rom_e ? rom_dout :
acia_e ? acia_dout :
via_e ? via_dout_r :
bus_data;
2. Provide additional address hold time, by clocking the 6502 core later
The relative phase of Phi2 and the output signals (address, data, rnw) is managed by the clken_ctr and the cpu_clken signal.
The MSB of the counter is used as Phi2 - consider that fixed.
The CPU is clocked when cpu_clken is asserted.
Code:
always @(posedge clk) begin
....
cpu_clken <= &clken_ctr; // active when all 1's
....
end
Consider CLKEN_BITS being 3:
Code:
clken_ctr phi2 cpu_clken address
110 1 0 XXXX
111 1 0 XXXX
000 0 1 XXXX
001 0 0 YYYY
010 0 0 YYYY
011 0 0 YYYY
100 1 0 YYYY
101 1 0 YYYY
So currently the address (and other outputs) changes (from XXXX to YYYY) one clk cycle after the falling edge of phi2.
It might be worth delaying this a bit to provide extra address hold time.
Currently we have:
Code:
always @(posedge clk) begin
....
cpu_clken <= &clken_ctr; // active when all 1's
....
end
This is the same as:
Code:
always @(posedge clk) begin
....
cpu_clken <= (clken_ctr == (2**CLKEN_BITS-1));
....
end
To add one more clk cycle of delay to the outputs you would use:
Code:
always @(posedge clk) begin
....
cpu_clken <= (clken_ctr == 0);
....
end
To add a further clk cycles of delay to the outputs you would use:
Code:
always @(posedge clk) begin
....
cpu_clken <= (clken_ctr == 1);
....
end
What I would suggest is:
Use a system clock of 50MHz, so each clk cycle is 20ns.
Use CLKEN_BITS of 4, so Phi2 is 50/(2**4) = 3.125MHz (a Phi2 cycle time of 320ns)
Adjust the clocking of the CPU core to give ~2 clk cycles (40ns) of address hold time.
Code:
always @(posedge clk) begin
....
cpu_clken <= (clken_ctr == 0);
....
end
This, together with registering the bus_data on the falling edge of Phi2, should give you a bus interface that is fairly similar to a 3-4MHz 6502.
I'll try and set this up myself on a breadboard tomorrow, if I can find a 65C22. If not, I'll have to order one, and it will be a few days.
Dave
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