While I thoroughly enjoyed putting together the wire-wrapped Garth-1, I was not totally satisfied with the results. I still have some questions about the preferred memory map, Phi2 write-qualification vs. chip-select qualification, and certain aspects of the 6502 bus timing. The wire-wrapped board is a little too noisy (without a ground-plane), an a little too hard to change on a whim. I did not sequence the wrapping wisely, and wound up with some deeply-buried wraps for things I may want to change...

To make experimentation easier, I slapped together a quick 4-layer PCB housing a W65C02, a VIA, a ZIF ROM socket and a skinny RAM. A 74xx00 provides some commonly used signals to make it easy to slap together a quick system. In anticipation of extensive experiments with a GAL, I provisioned space for a wire-wrap socket, as well as a fully ground-planed wire-wrap area. I routed all interesting signals to pads that can accommodate a wire-wrap post. I also provided pads for a variety of clock sources (full and half-can oscillator or 5x7mm SMT oscillator). Finally there is a space for a SOT223 reset supervisor.

To keep things simple I doubled up the inner layers as ground (power distribution is pretty minimal here) and placed all SMT components (including decoupling caps) sit on the back side of the board. I tried to provide a ground pads near signal pads.

The board is intended as a moving target, and I can upgrade/fine-tune it as needed, as the cost is minimal at JLCPCB. 5 boards should be arriving any day now and I will report on my progress on this thread...

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I am still trying to figure out the ideal 4-layer layout strategy. If the power plane is acting as a return path via bypass capacitors, the placement of bypass capacitors becomes much more of an issue. I am considering going back to my early experiments of placing capacitors directly into unplated holes (possibly increasing the thickness of the board to 1.8 or 2mm for a better fit) - I think Garth had some success with that. On the other hand, going to a thinner board makes more sense from the capacitive standpoint - 1.6mm boards have a 1.2mm central core...

I didn't mean to imply that doubling the ground layer is better than one - it was just easier in this case as routing and power distribution requirements are minimal, there is plenty of room, and all I really wanted was a good ground plane.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Huh, my memory is not very reliable these days. Sorry, Garth - for some reason I thought you were planting the caps into the substrate of your memory modules.

I was likely experimenting with a 0.8mm board as I remember the caps being a little too big. The flush end soldered easily, but the sticky-up end was too high to flow solder. It was also before I discovered the good flux, and soldering them was a bit of a hassle; things got easier after I hooked up an ohmmeter to the power and ground and checked it while soldering in the caps to avoid a short.

With a 4-layer board it may not be worth the hassle of routing power and ground from the inner layers out to the top/bottom of the unplated hole.

It may be one of those ideas that seems like a good one but in practice is not so great. But I am not yet taking it off my bucket list.

_________________
In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?