Hi guys, I'm building a TTL-based CPU designed to replicate the 6502 instruction set. Architecturally it's similar, too, but i'm not planning to be 100% compatible as this is just for fun and learning. I have a couple of design questions and I'm looking for opinions...

1) Instead of having the clock set the Ph1 and Ph2 control lines, what if I instead fed the clock signal only to the timing circuit and then set the clock lines using a couple of control lines? The advantages are:
* The control lines will be ready the instance the clock changes
* Reading the next set of control lines will be performed in parallel with the current phase
The disadvantages are:
* Are there any?

2) On Hanson's architectural diagram, there are several operations that are labeled as occurring during Ph1 or Ph2. I can understand one phase being called out if it's different from the default but why specifically label some actions both ways? What phase do the rest of the actions occur on, or is it expected that they can be either ph1 or ph2?

Thanks for the guidance,
Jason

Welcome!

I'm afraid I don't understand your first question - I would need to know more about the design discipline you're using and what you mean by the ph1 and ph2 control lines. The notable thing about the original NMOS 6502 is that it's a latch-based design with two non-overlapping clock phases. That's not the kind of thing we build these days, and if you change the fundamental clocking, you change the meaning of the clocks. It's possible to replicate the old style, and it's possible to build entirely in modern style, but I'm not sure about mixing and matching.

It would be good to see a block diagram of your design, especially if you can show the clock boundaries.

Thanks for responding - I really do appreciate it I also don't really have any diagrams yet but I hope this helps (sorry if I'm not being as helpful to you as you are to me!)

In my CPU, the top right board is the clock. This has two white lines coming out that go directly to the 'clock bus' lines which run down the center beside the power rails and data bus. The two clock lines represent phase1 and 2 of the clock, so phase1 is low, while phase2 is high, then they switch, then the clock cycle starts over. Throughout the board you'll see other white lines tying into the clock bus so they can receive either the phase1 or phase2 signals (still not sure about which each process should use, bu that's another question).

Bottom left is the timing circuit (the one with all the yellow lines and obviously the furthest from the clock - poor planning). Anyway, this reads from the clock bus and then updates the lines some 55-120ns after the clock line changes. The delay is due to the read time for the micro-code. My idea was to instead wire the clock directly into the timing circuit, thus leaving the clock bus lines untouched. When the micro code has been retrieved it would include two control lines to drive the clock bus lines. This means the clock will now change at the same time as the control lines.


Before:


After:

I've always struggled a bit with the fine details of clocking, so I like to try to be really clear.

If we remove all the combinatorial logic from your circuit, we are left with the sequential logic. Is that sensitive to levels, or to edges? If it's sensitive to levels, I like to call these elements latches, and I hope to see at least two non-overlapping clocks, although other schemes are possible. If the sequential logic is sensitive to edges, I like to call it flip-flops, or flops for short. Ideally, I like to see all flops are sensitive to the same edge - that's the current recommended approach in HDLs. If you have a mix of flops sensitive to rising and sensitive to falling, that's another valid possibility.

I think that makes about three major possibilities...

I am hoping that by 'clock bus' you mean 'a pair of clock signals' and by that you mean 'signals which control all the sequential elements. By this, I mean that I hope you don't also have a global clock, such that your 'clock bus' signals are actually combinatorial inputs.

I hope all this is helpful explanation of my thoughts - it's not intended as criticism.

Thanks BigEd, this all helps as any validation on what i'm building is useful.

Would it be any fun if I had all the right parts I've used flops as often as I can. In fact I think the only latches are the input latch and possibly the x/y registers (gated by the clock). I think maybe i'll revisit the latter so I can be all flops.

Yes: 'clock bus' means a pair of clock signals, non-overlapping
Yes: clock signals control all the sequential elements

The clock is global, triggered by a 55 or crystal (I plan to remove the 555 and use a clock divider 4040). There's no feedback from the circuit into the clock, so I assume that alleviates your concerns over the clock being combinatorial inputs?

Thanks, that sounds good. I wasn't sure from your earlier descriptions if you were sampling the 'clocks' with a master clock, to act when they were high (or low.)

If you have two non-overlapping clocks and a flop-only design you might be using as many as four edges to cause things to happen - or as few as two edges. Hopefully it's two, so for example all your flops act on the rising edge of their respective clock inputs. (Or the falling.)

Oh, the other thing in a modern design discipline is for all flops to have the actual global clock(s) as their clocks. If you are making control signals and then using those as clock, that starts getting scary fast.

It might be good if you could tabulate what happens in each phase of a simple instruction, and make sure that there's time for signals to be derived and to settle by the time they are needed. A very simple instruction like TXA, for example. And then a more complex one like ADC #1. As you know, you'll need at least 6 or 7 cycles for the most complex.

Yes. And please, please, please -- that block diagram! Which should show all the main flops and latches. Otherwise we spectators will have a murky time indeed trying to guess what you're up to.

Fun project!

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I'll see what I can do.