You might want to take a closer look at your schematic. There are (obviously) some missing components and such, but some basic things you should be doing would include:
- adding pullup resistors to CPU lines: Reset, NMI, IRQ, BE, RDY and SO.
- using the CPU Clock2 line to qualify your memory write line at a minimum.
Looking at your I/O decoding, it's overly complicated and far too many gate delays. Also, the way it's showing, it won't work either.
On the second page, you're using a 74HC137 (3-to-8 decoder) with a 'HC04 inverter to create a main I/O select line at $8000 (pin 15). This is an active low signal for I/O.
One the third page, you're using a 74LS32 quad OR gate cascaded to drive a 'HC04 inverter to provide an I/O select to the 74HC139 (2-to-4 decoder).
The problem here is, the IO_SEL line driving pin 2 of the 'LS32 is active low, and the signal needs to be active high. Also, all of the address lines (A8, A9, A10, A11) driving the OR gates are active high, so if ANY of those address lines are active, the output at pin 11 will be high, which feeds the 'HC04, which will drive an active low to the 'HC139. Also, when the IO_SEL line is inactive (high), your EXPIO_SEL line will be active. In short, you will be driving an I/O device active pretty much all the time, except when you have an active IO_SEL line and address lines A8 thru A11 are inactive.
I suggest you draw out your full memory map and include which lines need to be active high or low and the memory range they are active for. Also, not using A6 and A7, you would have 4 echoed selects at different memory ranges. You should also consult the various datasheets and start adding up the average propagation delays with all of the gates, inverters and decoders you're using. It's getting to be a pretty big number. You might want to simply come up with the list of I/O selects and widths you need for the various devices and work backwards from there.
Finally, a CF card in true IDE mode can present the same set of I/O registers as a standard IDE disk device. Here's the definitions for my interface which includes the upper latch for 16-bit data lines:
Code:
; Adding BIOS definitions for 16-bit IDE interface
; uses two addresses for Upper Byte Latch read / write
; uses eight addresses for Command Block Registers
; uses two addresses for Control Block Registers
;
IDE_16_READ .EQU RTC_IDE_BASE+$14 ;Upper byte Read address
IDE_16_WRITE .EQU RTC_IDE_BASE+$15 ;Upper byte Write address
;
; Adding BIOS definitions for IDE Controller (HARD DISK, Flash Module, etc.)
; Hardware Adapter provides a 16-bit IDE Port per:
; Seagate ATA Interface Reference Manual 36111-001, Rev. C (21st May 1993)
;
; Control Block Registers
IDE_ALT_STATUS .EQU RTC_IDE_BASE+$16 ;Alternate Status Register (READ)
IDE_DEV_CTRL .EQU RTC_IDE_BASE+$16 ;Device Control Register (WRITE)
IDE_DRV_ADDR .EQU RTC_IDE_BASE+$17 ;Drive Address Register (READ)
;
; Command Block Registers
IDE_DATA .EQU RTC_IDE_BASE+$18 ;Data Register (R/W)
IDE_ERROR .EQU RTC_IDE_BASE+$19 ;Error Register (READ)
IDE_FEATURE .EQU RTC_IDE_BASE+$19 ;Feature Register (WRITE)
IDE_SCT_CNT .EQU RTC_IDE_BASE+$1A ;Sector Count Register
IDE_SCT_NUM .EQU RTC_IDE_BASE+$1B ;Sector Number Register
IDE_CYL_LOW .EQU RTC_IDE_BASE+$1C ;Cylinder Low Register
IDE_CYL_HIGH .EQU RTC_IDE_BASE+$1D ;Cylinder High Register
IDE_DRV_HEAD .EQU RTC_IDE_BASE+$1E ;Drive/Head Register
IDE_STATUS .EQU RTC_IDE_BASE+$1F ;Status Register (READ)
IDE_COMMAND .EQU RTC_IDE_BASE+$1F ;Command Register (WRITE)
;
Hope this helps.
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