I did review 6502 undocmented opcodes from Commodore and Atari. Opcode on each $X2 is like halt or kill microprocessor. It does not say zero or one cycle is spent.

For example:

A9 C1 LDA #C1
02 KIL

First Cycle -- fetch opcode byte --> A9
Second Cycle -- fetch first operand byte --> C1
Third Cycle -- fetch opcode byte --> 02

During third cycle, KIL instruction is executed before it brings microprocessor to a full shut down or halt.

I wonder, it should be halt on either during second cycle or third cycle. Do you have idea? I am curious.


KIL (JAM) [HLT]
~~~~~~~~~~~~~~~
Stop program counter (processor lock up).
Status flags: -

Addressing |Mnemonics |Opc|Sz | n
------------|-----------|---|---|---
Implied |KIL |$02| 1 | -
Implied |KIL |$12| 1 | -
Implied |KIL |$22| 1 | -
Implied |KIL |$32| 1 | -
Implied |KIL |$42| 1 | -
Implied |KIL |$52| 1 | -
Implied |KIL |$62| 1 | -
Implied |KIL |$72| 1 | -
Implied |KIL |$92| 1 | -
Implied |KIL |$B2| 1 | -
Implied |KIL |$D2| 1 | -
Implied |KIL |$F2| 1 | -


Bryan

A KIL operation stops the processor because the internal PLA never signals an end-of-instruction. Thus, the processor doesn't actually stop, it just enters an endless loop waiting for a non-existant end-of-instruction signal. In theory, therefore, the instruction takes an infinite number of cycles.

After the 1st 7 cycles of a KIL instruction, the internal PLA will not activate any signals so at this point the processor is doing nothing. What happens in the first 7 cycles depends on the internal structure of the 6502 PLA. It is possible that internal registers are updated during these cycles.

If you wish to find out exactly what a 6502 does in a KIL instruction the following link may be helpfull

http://www.pagetable.com/?p=39

It is a discussion on how the 6502 handles undocumented op-codes.

_________________
Shift to the left,
Shift to the right,
Mask in, Mask Out,
BYTE! BYTE! BYTE!

>A KIL operation stops the processor because the internal PLA never >signals an end-of-instruction. Thus, the processor doesn't actually stop, >it just enters an endless loop waiting for a non-existant end-of->instruction signal. In theory, therefore, the instruction takes an infinite >number of cycles.

Let me support your theory.

$2000: A9 C1 LDA #C1
$2002: 02 Kill
$2003: EA NOP

Two cycles have passed to execute LDA #C1. During second cycle, PC increments to $2002

During third cycle, PC -- $2002 is on address bus. MPU is reading $02 at $2002 from RAM and places $02 on data bus. MPU fetches $02 as opcode from data bus. PC does not increment to $2003 and it is always staying at $2002.

During fourth cycle, the behavior is identical to third cycle. During fifth cycle, sixth cycle, and so forth are identical. Reading $02 at $2002 from RAM and places it on data bus. MPU causes to do endless loop with the same $2002 on address bus and $02 on data bus EACH ONE CYCLE forever.

Is theory correct?

>After the 1st 7 cycles of a KIL instruction, the internal PLA will not >activate any signals so at this point the processor is doing nothing. What >happens in the first 7 cycles depends on the internal structure of the >6502 PLA. It is possible that internal registers are updated during these >cycles.

The only way to really find out waht a 6502 does with a KIL instruction is to try it out with an actual 6502.

The PC will certainally increment after reading the op-code in, so if it outputs the PC onto the bus again it will be for the address after the instruction.

What else the 6502 does in the first 7 cycles of a KIL instruction is uncertain. It may even be different for 6502s from different manufacturers.

_________________
Shift to the left,
Shift to the right,
Mask in, Mask Out,
BYTE! BYTE! BYTE!

during first seven cycles look like interrupt vector after KIL instruction is executed. Did you use Logic Analyzer to test address bus and data bus on the MOS 6502 MPU chip? What did address bus and data bus look like during first seven cycles? After first seven cycles have passed, address bus and data bus are probably to be invalid or they always hold data on both address bus and data bus endless loop forever.

Let me show the list of 65C02 reserved instructions. During NOP is executed, two cycles are always spent, but not one cycle. It does not make sense. I get information from WDC 65C02 datasheet. Please give me the correct NOP cycles on 65C02. Thanks...

Function: Execution of invalid OpCodes
NMOS 6502: Some terminate only by reset. Results are undefined.
CMOS 65C02: All are NOPs (reserved for future use).
OpCode Bytes Cycles
02 2 2
22 2 2
42 2 2
62 2 2
82 2 2
C2 2 2
E2 2 2

X3 1 1
0B-BB 1 1
EB 1 1
FB 1 1

44 2 3

54 2 4
D4 2 4
F4 2 4

5C 3 8

DC 3 4
FC 3 4